LMK03200EVAL National Semiconductor, LMK03200EVAL Datasheet - Page 17

• Manufacturer Part Number: LMK03200EVAL
• Description: BOARD EVALUATION LMK03200
• Manufacturer: National Semiconductor

Specifications of LMK03200EVAL

• Main Purpose: Timing, Clock Conditioner
• Embedded: No
• Utilized Ic / Part: LMK03200
• Primary Attributes: 3 LVDS & 5 LVPECL Outputs, Integrated PLL & VCO
• Secondary Attributes: 3.15 V ~ 3.45 V Supply
• Silicon Manufacturer: National
• Silicon Core Number: LMK03200
• Kit Application Type: Clock & Timing
• Application Sub Type: Precision Clock Conditioner
• Kit Contents: Board, Cable
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The Bits/Pins tab shows some
o
Figure 14 - Bits & Pins tab
Program Bits
POWERDOWN
EN_Fout
OSCin_FREQ
PLL_MUX
DIV4
RESET
Vboost
VCO_R3_LF
VCO_R4_LF
VCO_C3_C4_LF
EN_CLKout0..7
PLL_N_DLY
PLL_R_DLY
0_DELAY_MODE
DLD_MODE2
FB_MUX
EN_CLKout_Global
Program Pins
GOE
SYNC*
TRIGGER
ther visual tabs like “PLL” and
L M K 0 3 2 0 0
Powers the part down.
Turns on the Fout pin for measuring the internal VCO.
Must be set to the OSCin frequency in MHz.
Programmable to many different values to support Lock Detect or aid
troubleshooting.
Shall be checked for OSCin frequencies greater than 20 MHz.
The registers can be defaulted by checking and unchecking RESET.
Software bits will not reflect this.
Increases Output Power on Clock Outputs
Internal
Enable CLKout bits from CLKout0 to CLKout7. Also accessible from Clock
Outputs tab.
Delays for PLL N and PLL R. Also on Clock Outputs Tab
Used to enable 0-Delay Mode, in the CodeLoader software, this will also
cause PLL_N to be reprogrammed.
Select alternate Digital Calibration Routine Complete mode in place of
Digital Lock Detect mode. To use select Digital Lock Detect on PLL_MUX.
Feedback from which clock output.
Enable all clock outs. If unselected then the EN_CLKouts are overridden
and the outputs are all disabled.
Set Global Output Enable to high or low logic level.
Set SYNC* pin to high or low logic level.
Set auxiliary trigger pin to high or low logic level.
loop filter values, also accessible from Clock Outputs tab.
of the internal registers which are not accessible from any of the
“Clock Outputs.” Right click on any of the bits for description.
E V A L U A T I O N
17
B O A R D
O P E R A T I N G
I N S T R U C T I O N S