ISL98003INZ-EVALZ Intersil, ISL98003INZ-EVALZ Datasheet - Page 17

• Manufacturer Part Number: ISL98003INZ-EVALZ
• Description: EVALUATION BOARD FOR ISL98003INZ
• Manufacturer: Intersil

Specifications of ISL98003INZ-EVALZ

• Main Purpose: Interface, Analog Front End (AFE)
• Embedded: No
• Utilized Ic / Part: ISL98003
• Primary Attributes: Triple 8-Bit ADC, 8x Oversampling
• Secondary Attributes: Automatic Black Level Compensation (ABLC™)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Listing
MEASUREMENT REGISTERS
ADDRESS
0x31
0x32
0x40
0x41
0x42
0x43
HSYNC/SOG Config,
(0x04)
Sync Polling Control, (0x00)
HSYNC Period MSB,
(read only)
HSYNC Period LSB,
(read only)
HSYNC Width MSB,
(read only)
HSYNC Width LSB,
(read only)
(DEFAULT VALUE)
REGISTER
(Continued)
17
BITS
3:0
7:0
7:0
7:0
7:0
4
5
6
0
1
2
3
4
5
6
7
Glitch Filter Width
Sync Glitch Filter Disable
SOG Hyst Disable
SOG LPF Disable
CH0 Polling
CH1 Polling
N/A
N/A
CH0 Connector Type
CH1 Connector Type
N/A
N/A
HSYNC Period MSB
HSYNC Period LSB
HSYNC Width MSB
HSYNC Width LSB
FUNCTION NAME
ISL98003
0: 16 crystal clocks
1: 17 crystal clocks
2: 1 crystal clocks
3: 2 crystal clocks
4: 3 crystal clocks (default)
5: 4 crystal clocks
6: 5 crystal clocks
7: 6 crystal clocks
8: 7 crystal clocks
9: 8 crystal clocks
10: 9 crystal clocks
11: 10 crystal clocks
12: 11crystal clocks
13: 12 crystal clocks
14: 13 crystal clocks
15: 14 crystal clocks
0: glitch filter enabled
1: glitch filter disabled
0: 40mV hysteresis enabled
1: 40mV hysteresis disabled
0: 14MHz SOG Low Pass Filter Enabled
1: 14MHz SOG Low Pass Filter Disabled
0: Enable
1: Disable
0: Enable
1: Disable
Set to 1
Set to 1
0: RGB DB15 (poll for HSYNC, CSYNC, and SOG)
1: Component (poll for SOG only)
0: RGB DB15 (poll for HSYNC, CSYNC, and SOG)
1: Component (poll for SOG only)
Set to 0
Set to 0
These registers report a 16-bit value containing the number of
crystal clocks inside a 16 consecutive HSYNC period window.
This means the 16-bit number will reflect one HSYNC period
with 1/16 LSB resolution - the last 4 -bits of the measurement
will be fractional.
These registers report a 16-bit value containing the number of
crystal clocks inside 16 consecutive HSYNC pulses. This
means the 16-bit number will reflect one HSYNC pulse width
with 1/16 LSB resolution - the last 4 bits of the measurement
will be fractional.
DESCRIPTION
September 12, 2008
FN6760.0