CLINK3V48BT-112 National Semiconductor, CLINK3V48BT-112 Datasheet - Page 15

• Manufacturer Part Number: CLINK3V48BT-112
• Description: KIT EVAL 48BIT DS90CR481/2/3/4
• Manufacturer: National Semiconductor

Specifications of CLINK3V48BT-112

• Main Purpose: Interface, Serializer, Deserializer (SERDES)
• Utilized Ic / Part: DS90CR481, DS90CR482, and DS90CR483
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

Calculating RSKM Link Margin
Receiver Skew Margin (RSKM) & Pair-to-Pair Skew
The main consideration for Channel Link SerDes performance over cable is pair-to-pair skew. Unlike other SerDes, Channel Link SerDes send data
and clock over multiple pairs, lowering the data rate per pair and reducing the normal concerns from ISI.
Channel Link SerDes can be thought of as being very high speed latches. As long as input setup and hold times are met, no data or bit errors
occur and data in will equal data out. The Channel Link serializer is like a normal latch that strobes data once or twice a clock cycle. Channel Link
SerDes deserializers, on the other hand, sample 7 bits every clock cycle making skew between the clock and data pairs very important to ensure
setup and hold times are met, i.e. the data sample strobes are aligned to the middle of the data bits. Determining if interconnect skew meets the
receiver setup and hold times is easy since the Channel Link deserializer datasheet provides a single specification called receiver skew margin
(RSKM) that indicates the maximum amount of skew and jitter the deserializer can tolerate.
If both RSKM-left and RSKM-right are given in the datasheet, use the smaller of the two.
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