CLINK3V48BT-112 National Semiconductor, CLINK3V48BT-112 Datasheet - Page 16

• Manufacturer Part Number: CLINK3V48BT-112
• Description: KIT EVAL 48BIT DS90CR481/2/3/4
• Manufacturer: National Semiconductor

Specifications of CLINK3V48BT-112

• Main Purpose: Interface, Serializer, Deserializer (SERDES)
• Utilized Ic / Part: DS90CR481, DS90CR482, and DS90CR483
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

RSKM is very similar to the receiver jitter tolerance specifications of other SerDes devices, except:
• RSKM already includes serializer data output jitter. Clock jitter is not included, however, and therefore TJCC must be subtracted out.
• RSKM is not only just a jitter tolerance specification but a “jitter plus pair-to-pair skew” tolerance specification.
The RSKM specification indicates how much skew and jitter the deserializer can tolerate, therefore, total pair-to-pair skew and clock plus data
jitter must be less than the RSKM specification for no bit errors:
Pair-to-pair cable skew is given by the cable manufacturers cable specification.
PCB layout skew can be simulated or measured but may be negligible in a carefully designed system.
Clock jitter is given by the TJCC datasheet spec and is 100 ps worst case. Only cycle-to-cycle clock jitter is important since the receiver uses the
previous clock cycle to latch in the current data cycle.
Data jitter from the serializer outputs is already contained in the RSKM specification, so only jitter contributed by the interconnect should be
considered. This jitter consists mainly inter-symbol interference (ISI) effects due to cable loss and can be measured on an eye pattern. For short
cables, ISI may be negligible. For systems with short cables and very low PCB layout skew, the link margin formula above can be reduced to
simply:
Parameter
Pair-to-Pair Skew
Clock Jitter = TJCC
Data Jitter Added by Cable = ISI
Receiver Skew Margin
Remaining Link Margin
16
pair-to-pair skew (cable plus PCB skew) + jitter (clock plus data jitter) < RSKM
Channel Link Operation
Calculating RSKM Link Margin Without Deskew
Application
Telecom System with Very Low Jitter Clocks
Systems with PC-Grade Clocks
+
+
+
=
-
RSKM - (pair-to-pair skew + TJCC)
Link Margin Without Deskew
Cable skew + TJCC (100 ps) < RSKM
Cable assembly + PCB skew
RSKM from datasheet
TJCC worst case is 100 ps
Short Cables
100 ps
≈ 0
where
TJCC Value
50 ps
100 ps
RSKM - (pair-to-pair skew + TJCC + ISI)
Cable assembly + PCB skew
Measure from eye pattern
RSKM from datasheet
Long Cables
100 ps