CLINK3V48BT-112 National Semiconductor, CLINK3V48BT-112 Datasheet - Page 17

• Manufacturer Part Number: CLINK3V48BT-112
• Description: KIT EVAL 48BIT DS90CR481/2/3/4
• Manufacturer: National Semiconductor

Specifications of CLINK3V48BT-112

• Main Purpose: Interface, Serializer, Deserializer (SERDES)
• Utilized Ic / Part: DS90CR481, DS90CR482, and DS90CR483
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

Cable pair-to-pair skew is often the limiting factor in Channel Link designs. Therefore, the DS90CR48x 48-bit Channel Link chipsets include a
feature to deskew the cable. After deskew operation is performed using these chipsets, only pair-to-pair skew that exceeds the deskew range of
the chipset must be subtracted from link margin. Therefore, the interconnect has design margin if remaining pair-to-pair skew after deskew plus
jitter is less than the RSKMD specification:
Pair-to-pair cable skew is the deskew range, RDR, of the receiver datasheet minus the total cable/connector/PCB interconnect skew. If RDR is
greater than the interconnect skew, then use 0 ps for pair-to-pair skew in the equation.
Clock jitter is given by the TJCC datasheet spec and is 100 ps worst case. Only cycle-to-cycle clock jitter is important since the receiver uses the
previous clock cycle to latch in the current data cycle.
Data jitter from the serializer outputs is already contained in the RSKM specification, so only jitter contributed by the interconnect should be
considered. This jitter consists mainly inter-symbol interference (ISI) effects due to cable loss and can be measured on an eye pattern. For short
cables, ISI may negligible and the receiver deskew range is large enough to fully deskew the interconnect. For systems with short cables where
RDR exceeds interconnect skew, the link should be able to operate at the chipset maximum frequency provided that PLLVCC noise is less than 100
mV P-P and the transmit clock jitter is on the order of 100 ps or less.
Parameter
Pair-to-Pair Skew
Clock Jitter = TJCC
Data Jitter Added by Cable = ISI
Receiver Skew Margin
Remaining Link Margin
pair-to-pair skew (amount exceeding deskew range) + jitter (clock plus data jitter) < RSKMD
Application
Telecom System with Very Low Jitter Clocks
Systems with PC-Grade Clocks
+
+
+
=
-
Sufficient margin should exist for
Link Margin With Deskew
max frequency operation
Calculating RSKM Link Margin With Deskew
RSKMD from datasheet
TJCC worst case is 100 ps
Short Cables
100 ps
≈ 0
≈ 0
where
TJCC Value
50 ps
100 ps
RSKMD - ((RDR -pair-to-pair skew) +
RDR - (Cable assembly + PCB skew)
Measure from eye pattern
RSKMD from datasheet
Long Cables
TJCC + ISI)
100 ps
1