EVB9221-MINI SMSC, EVB9221-MINI Datasheet - Page 103
![EVALUATION BOARD LAN9221-ABZJ](/photos/9/10/91030/evb9221-mini_sml.jpg)
EVB9221-MINI
Manufacturer Part Number
EVB9221-MINI
Description
EVALUATION BOARD LAN9221-ABZJ
Manufacturer
SMSC
Datasheet
1.LAN9221-ABZJ.pdf
(152 pages)
Specifications of EVB9221-MINI
Main Purpose
Interface, Ethernet Controller (PHY and MAC)
Embedded
No
Utilized Ic / Part
LAN9221
Primary Attributes
1 Port, 100BASE-TX/10BASE-T
Secondary Attributes
16-Bit, HP Auto-MDIX, Full and Half Duplex Support, 32-Bit CRC
Processor To Be Evaluated
LAN9221
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1074
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High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
SMSC LAN9221/LAN9221i
5.3.23
BITS
31
EPC Busy: When a 1 is written into this bit, the operation specified in the
EPC command field is performed at the specified EEPROM address. This
bit will remain set until the operation is complete. In the case of a read this
means that the host can read valid data from the E2P data register. The
E2P_CMD and E2P_DATA registers should not be modified until this bit is
cleared. In the case where a write is attempted and an EEPROM is not
present, the EPC Busy remains busy until the EPC Time-out occurs. At that
time the busy bit is cleared.
Note:
E2P_CMD – EEPROM Command Register
This register is used to control the read and write operations with the Serial EEPROM.
Offset:
EPC busy will be high immediately following power-up or reset.
After the EEPROM controller has finished reading (or attempting to
read) the MAC address from the EEPROM the EPC Busy bit is
cleared.
DESCRIPTION
B0h
DATASHEET
103
Size:
32 bits
TYPE
SC
Revision 2.7 (03-15-10)
DEFAULT
0
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