EVB9221-MINI SMSC, EVB9221-MINI Datasheet - Page 92

• Manufacturer Part Number: EVB9221-MINI
• Description: EVALUATION BOARD LAN9221-ABZJ
• Manufacturer: SMSC

Specifications of EVB9221-MINI

• Main Purpose: Interface, Ethernet Controller (PHY and MAC)
• Embedded: No
• Utilized Ic / Part: LAN9221
• Primary Attributes: 1 Port, 100BASE-TX/10BASE-T
• Secondary Attributes: 16-Bit, HP Auto-MDIX, Full and Half Duplex Support, 32-Bit CRC
• Processor To Be Evaluated: LAN9221
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1074

Revision 2.7 (03-15-10)
5.3.10
BITS
30-0
31
RX Data FIFO Fast Forward (RX_FFWD): Writing a ‘1’ to this bit causes
the RX data FIFO to fast-forward to the start of the next frame. This bit will
remain high until the RX data FIFO fast-forward operation has completed.
No reads should be issued to the RX data FIFO while this bit is high.
Note:
Reserved
In addition to the host-accessible FIFOs, the MAC Interface Layer (MIL) contains an additional 2K
bytes of TX, and 128 bytes of RX FIFO buffering. These sizes are fixed, and cannot be adjusted by
the host.
As space in the TX MIL (Mac Interface Layer) FIFO frees, data is moved into it from the TX data FIFO.
Depending on the size of the frames to be transmitted, the MIL can hold up to two Ethernet frames.
This is in addition to any TX data that may be queued in the TX data FIFO.
Conversely, as data is received by the LAN9221/LAN9221i, it is moved from the MAC to the RX MIL
FIFO, and then into the RX data FIFO. When the RX data FIFO fills up, data will continue to collect
in the RX MIL FIFO. If the RX MIL FIFO fills up and overruns, subsequent RX frames will be lost until
room is made in the RX data FIFO. For each frame of data that is lost, the RX Dropped Frames
Counter (RX_DROP) is incremented.
RX and TX MIL FIFO levels are not visible to the host processor. RX and TX MIL FIFOs operate
independent of the TX data and RX data and status FIFOs. FIFO levels set for the RX and TX data
and Status FIFOs do not take into consideration the MIL FIFOs.
RX_DP_CTRL—Receive Datapath Control Register
This register is used to discard unwanted receive frames.
Offset:
Please refer to section “Receive Data FIFO Fast Forward” on
page 64 for detailed information regarding the use of RX_FFWD.
DESCRIPTION
78h
DATASHEET
92
High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Size:
32 bits
TYPE
R/W
SC
RO
SMSC LAN9221/LAN9221i
DEFAULT
Datasheet
0b
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