EVAL-AD7622CBZ Analog Devices Inc, EVAL-AD7622CBZ Datasheet - Page 8

• Manufacturer Part Number: EVAL-AD7622CBZ
• Description: BOARD EVALUATION FOR AD7622
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7622CBZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 2M
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 70mW @ 2MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7622
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin
No.
1, 36,
41, 42
2, 44
3
4
5
6
7
8
9, 10
11, 12
13
Mnemonic
AGND
AVDD
DGND
BYTESWAP
OB/2C
WARP
NORMAL
SER/PAR
D[0:1]
D[2:3]
or DIVSCLK[0:1]
D4
or EXT/INT
Type
P
P
P
DI
DI
DI
DI
DI/O
DO
DI/O
DI/O
1
Description
Analog Power Ground.
Input Analog Power Pins. Nominally 2.5 V.
Digital Power Ground.
Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output
on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8].
Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary;
when low, the MSB is inverted resulting in a twos complement output from its internal shift register.
Conversion Mode Selection. When WARP = high and NORMAL = high, this selects wideband warp
mode with slightly improved linearity and THD. When WARP = high and NORMAL = low, this selects
warp mode. In either mode, these are the fastest modes; maximum throughput is achievable, and
a minimum conversion rate must be applied to guarantee full specified accuracy.
Conversion Mode Selection. When NORMAL = low and WARP = low, this input selects normal mode
where full accuracy is maintained independent of the minimum conversion rate.
Serial/Parallel Selection Input.
When SER/PAR = high, the serial interface is selected and some bits of the data bus are used as a
serial port; the remaining data bits are high impedance outputs.
When SER/PAR = low, the parallel port is selected.
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. These pins are always outputs, regardless of
the interface mode.
When SER/PAR = low, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.
When SER/PAR = high, serial clock division selection. When using serial master read after convert mode
(EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally generated
serial clock that clocks the data output. In other serial modes, these pins are high impedance outputs.
When SER/PAR = low, this output is used as Bit 4 of the parallel port data output bus.
When SER/PAR = high, serial clock source select. This input is used to select the internally generated
(master) or external (slave) serial data clock.
When EXT/INT = low, master mode. The internal serial clock is selected on SCLK output.
When EXT/INT = high, slave mode. The output data is synchronized to an external clock signal,
gated by CS, connected to the SCLK input.
NC = NO CONNECT
D2/DIVSCLK[0]
D3/DIVSCLK[1]
BYTESWAP
NORMAL
SER/PAR
OB/2C
WARP
AGND
DGND
AVDD
D0
D1
10
12
11
1
2
3
4
5
6
7
8
9
Figure 5. Pin Configuration
48 47 46 45 44
13 14 15 16 17 18 19 20 21 22 23 24
PIN 1
IDENTIFIER
Rev. 0 | Page 8 of 28
(Not to Scale)
TOP VIEW
AD7622
43 42 41 40
39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
AGND
CNVST
PD
RESET
CS
RD
DGND
BUSY
D15
D14
D13
D12