CDB5340 Cirrus Logic Inc, CDB5340 Datasheet

BOARD EVAL FOR CS5340 STEREO ADC

CDB5340

Manufacturer Part Number
CDB5340
Description
BOARD EVAL FOR CS5340 STEREO ADC
Manufacturer
Cirrus Logic Inc
Datasheets

Specifications of CDB5340

Number Of Adc's
1
Number Of Bits
24
Sampling Rate (per Second)
192k
Data Interface
Serial
Inputs Per Adc
2 Single
Power (typ) @ Conditions
180mW @ 5 V
Voltage Supply Source
Analog and Digital
Operating Temperature
-10°C ~ 70°C
Utilized Ic / Part
CS5340
Product
Audio Modules
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
598-1544
Features
Cirrus Logic, Inc.
www.cirrus.com
Demonstrates recommended layout and
CS8406 generates S/PDIF, and EIAJ-340
Requires only an analog signal source and
grounding arrangements
compatible digital audio
power supplies for a complete Analog-to-
Digital-Converter system
ANALOG
INPUT
Evaluation Board for CS5340
CS5340
Copyright
(All Rights Reserved)
AND DATA
CLOCKS
I/O FOR
Cirrus Logic, Inc. 2003
Description
The CDB5340 evaluation board is an excellent means
for quickly evaluating the CS5340 24-bit, stereo A/D con-
verter. Evaluation requires a digital signal analyzer, an
analog signal source, and a power supply.
Also included is a CS8406 digital audio interface trans-
mitter
compatible audio data. The digital audio data is available
via RCA phono and optical connectors.
ORDERING INFORMATION
CDB5340
which
TRANSMITTER
AES/EBU
CS8406
S/PDIF
generates
Evaluation Board
S/PDIF,
CDB5340
and
OUTPUT
S/PDIF
DS601DB1
EIAJ-340
JUL ‘03
1

Related parts for CDB5340

CDB5340 Summary of contents

Page 1

... INPUT Cirrus Logic, Inc. www.cirrus.com Description The CDB5340 evaluation board is an excellent means for quickly evaluating the CS5340 24-bit, stereo A/D con- verter. Evaluation requires a digital signal analyzer, an analog signal source, and a power supply. Also included is a CS8406 digital audio interface trans- ...

Page 2

... Figure 7. Top Layer Silkscreen ..................................................................................................... 11 Figure 8. Top Layer ...................................................................................................................... 12 Figure 9. Bottom Layer................................................................................................................. 13 LIST OF TABLES Table 1. System Connections ........................................................................................................ 4 Table 2. CDB5340 Jumper and Switch Settings ............................................................................ 4 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (" ...

Page 3

... The evaluation board has been designed to allow interfacing to external systems via the 10-pin header, J11. The schematic for the clock/data input/output is shown in The CDB5340 allows some flexibility as to the generation of the clocks. When the CS5340 and CS8406 are in slave mode, the SCLK and LRCK must be provided via the header, J11. MCLK can be generated from the on-board oscillator provided via the header, J11 as determined by the DIP switch, S2 ...

Page 4

... J11 Input/Output for clocks/data S1 Reset for the CDB5340 S2 CDB5340 Configuration Table 2. CDB5340 Jumper and Switch Settings * denotes default factory settings 4 SIGNAL PRESENT +3.3V to +5V power for the CS5340 +2.5V to +5V power for the CS5340 Ground connection from power supply + 5 Volt power ...

Page 5

... DS601DB1 CDB5340 5 ...

Page 6

... CDB5340 DS601DB1 ...

Page 7

... DS601DB1 CDB5340 7 ...

Page 8

... CDB5340 DS601DB1 ...

Page 9

... DS601DB1 CDB5340 9 ...

Page 10

... CDB5340 DS601DB1 ...

Page 11

... DS601DB1 CDB5340 CDB5340 11 ...

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... CDB5340 DS601DB1 ...

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... DS601DB1 CDB5340 13 ...

Page 14

CDB4398 ...

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