HI5714EVAL Intersil, HI5714EVAL Datasheet

HI5714EVAL

Manufacturer Part Number

HI5714EVAL

Description

EVALUATION PLATFORM HI5714

Manufacturer

Intersil

Datasheets

1.HI57144CBZ.pdf (14 pages)

2.HI5714EVAL.pdf (11 pages)

Specifications of HI5714EVAL

Number Of Adc's

Number Of Bits

Sampling Rate (per Second)

75M

Data Interface

Parallel

Inputs Per Adc

1 Single Ended

Input Range

2.7 Vpp

Power (typ) @ Conditions

325mW @ 75MSPS

Voltage Supply Source

Analog and Digital

Operating Temperature

0°C ~ 70°C

Utilized Ic / Part

HI5714

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

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Description

The HI5714 evaluation board was designed to easily allow a

user to evaluate the performance of the HI5714 8-bit

75 MSPS Analog-to-Digital converter (ADC). The board

includes clock driver circuitry, reference voltage generators,

two input options and a reconstruct DAC. A block diagram of

the evaluation board is shown in Figure 3.

HI5714 Theory of Operation

The HI5714 design utilizes a folding and interpolating

architecture. This architecture reduces the number of

comparators, reference taps, and latches in comparison to a

full parallel flash converter, and as a result reduces power

requirements, die size and cost. A full parallel 8-bit flash

converter requires 255 comparators, 255 references and

255 latches, while the HI5714 utilizes only 16 comparators,

16 references and 16 latches.

A folding A/D converter operates basically like a 2 step

subranging converter by using 2 lower resolution converters

to do a course and subranged fine conversion. The major

difference in the folding technique is that the folding

amplifiers are used to do the fine conversion in parallel

with the course conversion, where the fine and course

conversions are done in a sequential mode for a

conventional subranging converter. The folding architecture

uses only the folding amplifiers, voltage comparators, flip-

flops and decoding circuits. Sample and hold and DAC

circuits are not required.

A folding amplifier is a number of parallel differential pairs

with interconnected outputs as shown in Figure 1. The

folding ratio is the number of differential pairs used in the

amplifier, which is 16 for the HI5714. When compared to a

traditional straight flash architecture, one folding amplifier

with a folding ratio of 16 replaces 16 input comparators.

Assuming no interpolation were to be performed, the number

of folding amplifiers necessary to implement an 8-bit

conversion (using a folding ratio of 16) would be DC at 16.

FIGURE 1. FOLDING AMPLIFIER WITH A FOLDING RATIO OF 2

Application Note

1-888-INTERSIL or 321-724-7143

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Using the HI5714 Evaluation Board

Features

• HI5714 Analog to Digital Converter

• External Reference

• Two Analog Inputs: One AC Coupled, One DC Coupled

• Reconstruct DAC: HI5721

• Buffered Digital Outputs

The interpolation technique further reduces the number of

necessary amplifiers by using passive elements to derive the

remaining signals. Interpolation (as seen in Figure 2) takes

advantage of the overlap between two adjacent amplifiers

and uses resistor taps to fill in the gaps (thereby replacing

three out of every four amplifiers with resistors). Signal

distortion introduced by interpolation can be ignored as only

the zero crossing is of importance.

As stated earlier in this section, the HI5714 uses a folding

ratio of 16 (16 latched comparators) with an interpolation

ratio of 4 (4 folding amplifiers). These 16 latched

comparators in turn are decoded into 32 ROM enables to

provide the 5 LSBs of the converter. There are 8 subranging

sections of the input voltage range which perform the coarse

conversion and provide the 3 MSBs of the device.

The bias current generator is based on a simple band gap

reference which provides a typical variation of 1% over the

full temperature range.

The operation of the part is depicted in the timing diagram in

Figure 4. There is a 1 cycle clock delay from the analog input

sampling point to the corresponding digital output data.

FIGURE 2. INTERPOLATED AMPLIFIER OUTPUTS

November 2002

All other trademarks mentioned are the property of their respective owners.

Intersil (and design) is a registered trademark of Intersil Americas Inc.

Author: Juan C. Garcia

AN9517.1

Related parts for HI5714EVAL

HI5714EVAL Summary of contents

Page 1

... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 321-724-7143 All other trademarks mentioned are the property of their respective owners. AN9517.1 Author: Juan C. Garcia Intersil (and design registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved ...

Page 2

CLK 1.2V REF ANALOG IN1 (DC) ANALOG IN2 (AC) +5VA CE CLOCK INPUT ANALOG INPUT DATA (D0-D7) OUTPUTS Power Supplies and Layout The HI5714 Evaluation Board is a four layer board with a layout optimized for the best performance for ...

Page 3

Table 1 lists the operating conditions for the power supplies. TABLE 1. POWER SUPPLIES POWER SUPPLY MIN TYP +5VA +4.75V +5.0V +5.25V -5.2VA -5.3V -5.2V +5VD +4.75V +5.0V +5.25V +12V +10V +12V -12V -10V -12V Reference Circuit For the following ...

Page 4

Control Amplifier to provide adequate drive for the segmented current cells and the R2/R resistor ladder. Reference Out (REF OUT) should be connected to the Control Amplifier Input (CTRL AMP IN). The Control Amplifier Output (CTRL AMP OUT) should be ...

Page 5

Figure 9 shows the test system used to do dynamic testing on the HI5714. The clock (CLK) and analog input (AIN) signal sources are derived from low phase noise HP8662A generators that are phase locked to each other ...

Page 6

R1 6.8K GAIN + 10µF ICL8069 10K C10 0.1 P3 10K C4 0 IN1 681 R8 88 IN2 + R5 10µF 51 R10 1K P4 10K 6 Application Note 9517 ...

Page 7

Application Note 9517 7 ...

Page 8

ITEM QUANTITY 1 1 CONN1 2 7 C1, C6, C11, C12, C13, C14, C15 3 4 C2, C9, C30, C31 4 7 C3, C8, C17, C22, C26, C28, C29 4a 8 C4, C10, C20, C21, C23-C25, C27 ...

Page 9

Application Note 9517 FIGURE 12. SILKSCREEN FIGURE 13. COMPONENT LAYER 9 ...

Page 10

Application Note 9517 FIGURE 14. POWER LAYER FIGURE 15. GROUND LAYER 10 ...

Page 11

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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