ADC12040EVAL National Semiconductor, ADC12040EVAL Datasheet - Page 13

• Manufacturer Part Number: ADC12040EVAL
• Description: BOARD EVALUATION FOR ADC12040
• Manufacturer: National Semiconductor

Specifications of ADC12040EVAL

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 40M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 340mW @ 40MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC12040
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Functional Description
Operating on a single +5V supply, the ADC12040 uses a
pipeline architecture and has error correction circuitry to help
ensure maximum performance. The differential analog input
signal is digitized to 12 bits.
The reference input is buffered to ease the task of driving that
pin and the output word rate is the same as the clock fre-
quency. The analog input voltage is acquired at the rising
edge of the clock and the digital data for a given sample is
delayed by the pipeline for 6 clock cycles.
A logic high on the power down (PD) pin reduces the con-
verter power consumption to 40 mW.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC12040:
V
within the limits of 0V to V
1.1 Analog Inputs
The ADC12040 has two signal input pins, V
forming a differential input pair, and one reference input pin,
V
1.2 Reference Pins
The ADC12040 is designed to operate with a 2.0V reference,
but performs well with reference voltages in the range of 1.0V
to 2.2V. Lower reference voltages will decrease the signal-to-
noise ratio (SNR). Increasing the reference voltage (and the
input signal swing) beyond 2.2V will degrade THD for a full-
scale input
It is important that all grounds associated with the reference
voltage and the input signal make connection to the ground
plane at a single point to minimize the effects of noise currents
in the ground path.
The three Reference Bypass Pins (V
made available for bypass purposes only. These pins should
each be bypassed to ground with a 0.1 µF capacitor. Smaller
capacitor values will allow faster recovery from the power
down mode, but may result in degraded noise performance.
DO NOT LOAD these pins.
1.3 Signal Inputs
The signal inputs are V
defined as
Figure 2 shows the expected input signal range.
Note that the common mode input voltage range is 1V to 3V
with a nominal value of V
between ground and 4V.
The Peaks of the individual input signals (V
should each never exceed the voltage described as
REF
REF
4.75V
V
2.35V
100 kHz
1.0V
0.5V
0V
D
.
= V
≤
and V
≤
≤
V
≤
≤
A
IN
V
V
V
V
≤
REF
CM
≤
CM
A
DR
f
(V
CLK
≤
≤
≤
must be such that the signal swing remains
≤
A
5.25V
3.0V
2.2V
V
≤
− 1.0V)
D
50 MHz
V
IN
IN
= (V
A
+ and V
/2. The input signals should remain
A
.
IN
+) – (V
IN
−. The input signal, V
IN
RP
−)
, V
RM
IN
IN
and V
+ and V
+ and V
RN
) are
IN
IN
IN
, is
−,
−)
13
to maintain THD and SINAD performance.
The ADC12040 performs best with a differential input with
each input centered around a V
swing at V
the reference voltage or the output data will be clipped. The
two input signals should be exactly 180° out of phase from
each other and of the same amplitude. For single frequency
inputs, angular errors result in a reduction of the effective full
scale input. For a complex waveform, however, angular errors
will result in distortion.
For angular deviations of up to 10 degrees from these two
signals being 180 out of phase, the full scale error in LSB can
be described as approximately
Where dev is the angular difference, in degrees, between the
two signals having a 180° relative phase relationship to each
other (see Figure 3). Drive the analog inputs with a source
impedance less than 100Ω.
FIGURE 3. Angular Errors Between the Two Input Signals
For differential operation, each analog input signal should
have a peak-to-peak voltage equal to the input reference volt-
age, V
age, V
TABLE 1. Input to Output Relationship – Differential Input
V
V
V
V
CM
CM
CM
CM
CM
REF
V
V
− V
− V
+ V
+ V
FIGURE 2. Expected Input Signal Range
.
CM
IN
, and be centered around a common mmode volt-
IN
+
REF
REF
REF
REF
+ and V
E
Will Reduce the Output Level
/2
/4
/2
/2
V
FS
IN
+, V
= 4096 ( 1 - sin (90° + dev))
IN
− each should not exceed the value of
IN
V
V
V
V
− = V
CM
CM
CM
CM
V
+ V
+ V
V
− V
− V
REF
CM
IN
CM
−
REF
REF
REF
RE/2F
+ V
. The peak-to-peak voltage
/2
/4
/4
CM
20014812
≤
20014811
0000 0000 0000
0100 0000 0000
1000 0000 0000
1100 0000 0000
1111 1111 1111
4V
Output
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