ADC12040EVAL National Semiconductor, ADC12040EVAL Datasheet - Page 8

• Manufacturer Part Number: ADC12040EVAL
• Description: BOARD EVALUATION FOR ADC12040
• Manufacturer: National Semiconductor

Specifications of ADC12040EVAL

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 40M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 340mW @ 40MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC12040
• Lead Free Status / RoHS Status: Not applicable / Not applicable

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Note 14: I
V
supply voltage, C
Note 15: Excludes I
Specification Definitions
APERTURE DELAY is the time after the rising edge of the
clock to when the input signal is acquired or held for conver-
sion.
APERTURE JITTER (APERTURE UNCERTAINTY) is the
variation in aperture delay from sample to sample. Aperture
jitter manifests itself as noise in the output.
CLOCK DUTY CYCLE is the ratio of the time during one cycle
that a repetitive digital waveform is high to the total time of
one period. The specification here refers to the ADC clock
input signal.
COMMON MODE VOLTAGE (V
present at both signal inputs to the ADC.
CONVERSION LATENCY See PIPELINE DELAY.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02
and says that the converter is equivalent to a perfect ADC of
this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It is the difference between the Positive Full
Scale Error and the Negative Full Scale Error:
INTEGRAL NON LINEARITY (INL) is a measure of the de-
viation of each individual code from a line drawn from negative
full scale (½ LSB below the first code transition) through pos-
itive full scale (½ LSB above the last code transition). The
deviation of any given code from this straight line is measured
from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the intermodulation
products to the total power in the original frequencies. IMD is
usually expressed in dBFS.
MISSING CODES are those output codes that will never ap-
pear at the ADC outputs. The ADC12040 is guaranteed not
to have any missing codes.
NEGATIVE FULL SCALE ERROR is the difference between
the actual first code transition and its ideal value of ½ LSB
above negative full scale (−V
OFFSET ERROR is the difference between the two input
voltages [ (V
code 2047 to 2048.
DR
Gain Error = Pos. Full Scale Error − Neg. Full Scale Error
, and the rate at which the outputs are switching (which is signal dependent). I
DR
is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage,
IN
n
+) – (V
is total capacitance on the output pin, and f
DR
. See note 14.
IN
−) ] required to cause a transition from
REF
).
CM
) is the d.c. potential
n
is the average frequency at which that pin is toggling.
8
DR
=V
OUTPUT DELAY is the time delay after the rising edge of the
clock before the data update is presented at the output pins.
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and when that data is pre-
sented to the output driver stage. Data for any given sample
is available at the output pins the Pipeline Delay plus the Out-
put Delay after the sample is taken. New data is available at
every clock cycle, but the data lags the conversion by the
pipeline delay.
POSITIVE FULL SCALE ERROR is the difference between
the actual last code transition and its ideal value of 1½ LSB
below the reference voltage.
POWER SUPPLY REJECTION RATIO (PSRR) is a measure
of how well the ADC rejects a change in the power supply
voltage. For the ADC12040, PSRR1 is the ratio of the change
in Full-Scale Error that results from a change in the d.c. power
supply voltage, expressed in dB. PSRR2 is a measure of how
well an a.c. signal riding upon the power supply is rejected at
the output.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the sam-
pling frequency, not including harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or
SINAD) Is the ratio, expressed in dB, of the rms value of the
input signal to the rms value of all of the other spectral com-
ponents below half the clock frequency, including harmonics
but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB, between the desired signal amplitude
to the amplitude of the peak spurious spectral component,
where a spurious spectral component is any signal present in
the output spectrum that is not present at the input and may
or may not be a harmonic.
TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-
pressed in dB or dBc, of the rms total of the first nine harmonic
components to the rms value of the input signal. THD is cal-
culated as
where F
quency and f
harmonic frequencies in the output spectrum.
DR
(C
0
x f
1
0
is the RMS power of the fundamental (output) fre-
+ C
1
2
x f
through f
1
+....C
11
x f
10
11
are the RMS power of the first 9
) where V
DR
is the output driver power