ADC12040EVAL National Semiconductor, ADC12040EVAL Datasheet - Page 17

• Manufacturer Part Number: ADC12040EVAL
• Description: BOARD EVALUATION FOR ADC12040
• Manufacturer: National Semiconductor

Specifications of ADC12040EVAL

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 40M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 340mW @ 40MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC12040
• Lead Free Status / RoHS Status: Not applicable / Not applicable

exhibit high transients that could add noise to the conversion
process. To prevent this from happening, the DR GND pins
should NOT be connected to system ground in close proximity
to any of the ADC12040's other ground pins.
Capacitive coupling between the typically noisy digital circuit-
ry and the sensitive analog circuitry can lead to poor perfor-
mance. The solution is to keep the analog circuitry separated
from the digital circuitry, and to keep the clock line as short as
possible.
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have signif-
icant impact upon system noise performance. The best logic
family to use in systems with A/D converters is one which
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane volume.
Generally, analog and digital lines should cross each other at
90° to avoid crosstalk. To maximize accuracy in high speed,
high resolution systems, however, avoid crossing analog and
digital lines altogether. It is important to keep clock lines as
short as possible and isolated from ALL other lines, including
other digital lines. Even the generally accepted 90° crossing
should be avoided with the clock line as even a little coupling
can cause problems at high frequencies. This is because oth-
er lines can introduce jitter into the clock line, which can lead
to degradation of SNR. Also, the high speed clock can intro-
duce noise into the analog chain.
Best performance at high frequencies and at high resolution
is obtained with a straight signal path. That is, the signal path
through all components should form a straight line wherever
possible.
Be especially careful with the layout of inductors. Mutual in-
ductance can change the characteristics of the circuit in which
they are used. Inductors should not be placed side by side,
even with just a small part of their bodies beside each other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any ex-
FIGURE 7. Example of a Suitable Layout
17
employs non-saturating transistor designs, or has low noise
characteristics, such as the 74LS, 74HC(T) and 74AC(T)Q
families. The worst noise generators are logic families that
draw the largest supply current transients during clock or sig-
nal edges, like the 74F and the 74AC(T) families. In high
speed circuits, however, it is often necessary to use these
higher speed devices. Best performance requires careful at-
tention to PC board layout and to proper signal integrity
techniques.
The effects of the noise generated from the ADC output
switching can be minimized through the use of 47Ω to 100Ω
resistors in series with each data output line. Locate these
resistors as close to the ADC output pins as possible.
ternal component (e.g., a filter capacitor) connected between
the converter's input pins and ground or to the reference input
pin and ground should be connected to a very clean point in
the ground plane.
Figure 7 gives an example of a suitable layout. A single
ground plane is recommended with separate analog and dig-
ital power planes. The analog and digital power planes should
NOT overlap each other. All analog circuitry (input amplifiers,
filters, reference components, etc.) should be placed over the
analog power plane. All digital circuitry and I/O lines should
be placed over the digital power plane. Furthermore, all com-
ponents in the reference circuitry and the input signal chain
that are connected to ground should be connected together
with short traces and enter the ground plane at a single point.
All ground connections should have a low inductance path to
ground.
6.0 DYNAMIC PERFORMANCE
To achieve the best dynamic performance, the clock source
driving the CLK input must be free of jitter. Isolate the ADC
clock from any digital circuitry with buffers, as with the clock
tree shown in Figure 8.
As mentioned in Section 5.0, it is good practice to keep the
ADC clock line as short as possible and to keep it well away
from any other signals. Other signals can introduce jitter into
the clock signal, which can lead to reduced SNR perfor-
mance, and the clock can introduce noise into other lines.
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