ADC14DS105KARB/NOPB National Semiconductor, ADC14DS105KARB/NOPB Datasheet - Page 10

• Manufacturer Part Number: ADC14DS105KARB/NOPB
• Description: BOARD EVAL FOR ADC14DS105KARB
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC14DS105KARB/NOPB

• Design Resources: ADC14DS105KARB Ref Design
• Number Of Adc's: 2
• Number Of Bits: 14
• Sampling Rate (per Second): 105M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Power (typ) @ Conditions: 1W @ 105MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC14DS105
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC14DS105KARB

5.3 ADC Reference
The internal 1.2V reference on the ADC14DS105 is
used
recommended
ADC14DS105.
5.4 Clock Input
The ADC clock used to sample the analog inputs is
generated using a VCXO controlled by the LMK02000
Precision Clock Conditioner. The LMK02000 is gives
the user an ultra-low noise phase-locked loop (PLL)
paired with a clock distribution section that provides 5
LVPECL outputs and 3 LVDS outputs (all differential).
Though not used in this design, each clock output
channel on the LMK02000 contains a divider block and
delay adjustment clock. The LMK02000 is typically
paired with a low jitter VCXO, in this case the Crystek
N
in
this
Figure 11. LMK02000 Phase Noise Performance, 100 MHz, Measured at CLKout4
reference
reference
-100
-110
-120
-130
-140
-150
-160
100
Reference Osc
design.
configuration
Figure 10. Clocking Circuit for ADC14DS105KARB
Measured Phase Noise of the LMK02000, F_carrier = 100 MHz
1000
ADC14DS105KARB Reference Design Board User’s Guide
This
LMK02000
for
is
10000
the
the
Offset (Hz)
- 10 -
VCXO
model CVHD-950X-100.0, which provides a single-
ended CMOS clock driving the ADC clock input. On the
ADC14DS105KARB evaluation boad, the LMK02000
PLL locks this VCXO to a 25 MHz reference oscillator
(Connor-Winfield model CWX823). Figure 10 shows a
block
ADC14DS105KARB reference board.
counters, phase detector and charge pump of the
LMK02000
microcontroller board as discussed in Section 4.4 of
this guide.
The LMK02000 achieves 128 fs RMS jitter (integrated
from 100 Hz to 20 MHz). Figure 11 illustrates the phase
noise performance of the clock, measured at CLKout4
of the LMK02000.
The single-ended clock signal from the VCXO is
applied to the CLK input on the ADC14DS105.
100000
diagram
are
1000000
of
ADC
programmed
the
Phase Noise
clocking
10000000
using
www.national.com
circuit
The PLL
the
on
Rev 0.2
PIC
the