ADC14DS105KARB/NOPB National Semiconductor, ADC14DS105KARB/NOPB Datasheet - Page 5

• Manufacturer Part Number: ADC14DS105KARB/NOPB
• Description: BOARD EVAL FOR ADC14DS105KARB
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC14DS105KARB/NOPB

• Design Resources: ADC14DS105KARB Ref Design
• Number Of Adc's: 2
• Number Of Bits: 14
• Sampling Rate (per Second): 105M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Power (typ) @ Conditions: 1W @ 105MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC14DS105
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC14DS105KARB

4.3 Evaluation Board Jumper Positions
1. JP1 should have a jumper installed to provide
If the SPI_EN jumper is not in place, then the
ADC14DS105
ADC14DS105KARB
configured as follows. Please refer to Figure 1 for the
exact jumper locations.
1. The DLC pin jumper selects the Dual Lane
N
power to the PIC microcontroller board used for
programming the LMK02000 registers.
Remove JP1 if using Codeloader to program the
LMK02000 (see Section 5.5 of this guide).
configuration. When the jumper is in place, the pin
is asserted HIGH and all data is sourced on a
single lane (SD1_X) for each channel. When the
jumper is removed, both channels operate in dual-
lane mode and the SD1_X and SD0_X outputs
both carry data. This control is disabled when the
Figure 3. SPI Software Control Panel
Only change
this field
ADC Control Jumpers
is
under
board
pin
jumpers
control,
ADC14DS105KARB Reference Design Board User’s Guide
should
and
the
be
- 5 -
Table 1. DLC Mode Jumper Description (Note: This
2. The word-alignment-mode (WAM) jumper on the
Table 2. WAM Jumper Description (Note: This jumper
3. The PDA and PDB jumpers are used to place the
Table 3. ADC Power-down Jumper Configuration (PDA
SPI_EN jumper is installed (SPI is active), as the
DLC mode is controlled through the SPI interface.
front of the board controls the alignment of the
sample data words at the ADC outputs. If the DLC
mode is single-lane, this jumper must NOT be
installed (WAM state is LOW). When the DLC
mode is dual-lane (DLC jumper is removed), and
the WAM jumper is not installed, the data samples
at the SD1_X/SD0_X outputs are offset by one-half
sample word. Likewise, when the WAM jumper is
installed for dual-lane mode, the data words on
SD1_X/SD0_X are time aligned with one another.
This pin has no effect when SPI_EN jumper is
installed (SPI is active), as the WAM mode is then
controlled through the SPI interface.
ADC14DS105 converters into either power-down or
normal operation mode. Table 1 below shows how
to select between the power-down modes.
If both Channel A and Channel B are powered
down at the same time, the ADC14DS105KARB
reference board must be power-cycled to recover.
Jumper
position
OPEN
INSTALLED
Jumper
position
OPEN
INSTALLED
PDx Jumper Settings
Open
1-2
jumper has no effect when the SPI_EN jumper
is installed)
and PDB)
has no effect when the SPI_EN jumper is
installed)
Description
Both
outputs operate in dual-lane
mode
ADC LVDS channel outputs
operate in single-lane mode
Description
When operating in single lane
mode (DLC jumper is installed),
this
installed
When operating in dual lane
mode, the data samples are
offset by one-half word.
When operating in dual lane
mode, the data samples are
aligned.
jumper
ADC
Mode
Normal Operation
Power-down
must
LVDS
www.national.com
NOT
channel
Rev 0.2
be