ISL6521EVAL1Z Intersil, ISL6521EVAL1Z Datasheet - Page 3

• Manufacturer Part Number: ISL6521EVAL1Z
• Description: EVALUATION BOARD 1 ISL6521
• Manufacturer: Intersil

Specifications of ISL6521EVAL1Z

• Main Purpose: DC/DC, Step Down with LDO
• Outputs And Type: 4, Non-Isolated
• Voltage - Output: 1.5V, 2.5V, 3.3V, 1.8V
• Current - Output: 5A, 1A, 1A, 120mA
• Voltage - Input: 4.5 ~ 5.5V
• Regulator Topology: Buck
• Frequency - Switching: 300kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6521
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

The ISL6521EVAL1 is designed with a room temperature
overcurrent trip point of 7A. The trip point is set by the
OCSET resistor and is established relative to the r
the upper MOSFET. See the product datasheet for additional
information on setting this trip point.
The linear controllers feature undervoltage protection which
also provide overcurrent protection. A low impedance short on
a linear output will cause the output voltage to sag. When the
output voltage drops below 70% of the output voltage set point,
the linear controller shuts down. The linear controller then
enters a wait period equivalent to three soft-start intervals. A
soft-start interval follows and if the undervoltage condition
remains, the linear controller will shutdown during soft-start.
Until successful, the linear controller will attempt to restart the
output in the same hiccup mode style outlined above.
Shutdown on any one output does not shutdown all outputs.
Transient Response
FPGA transient specifications vary depending on overall
gate usage. The ISL6521EVAL1 is designed to meet a load
step of 5A with a slew rate of 2.5A/µs. During a transient, the
FPGA core voltage (VOUT1) must not exceed ±50mV of
+1.5V. The leading edge transient response of the
ISL6521EVAL1 to the aforementioned load is shown in
Figure 6. The core voltage waveform is offset to +1.5V.
The core voltage sags as the inductor current begins to slew
in response to the changing load current. The controller
detects the new load level by the drop in output voltage and
responds by increasing the pulse width to the upper
MOSFET. The bulk output capacitors support the load as the
inductor slews. The increase in duty cycle can be seen
looking at the PHASE waveform just before, during, and
after the transient edge reaches 5A. The inductor current
rapidly increases to meet the new demand, supplying an
increasing portion of the load. The output voltage returns to
the +1.5V set point as the inductor picks up the load again.
FIGURE 6. LEADING EDGE TRANSIENT RESPONSE
1.5V
10µs/div
3
VOUT1, 50mV/div
PHASE, 5V/div
IOUT1, 5A/div
Application Note 1247
DS(on)
of
In Figure 7, the output voltage rises in response to the
removal of load and the inductor begins to slew down to the
original load level. The controller detects the output voltage
rise and immediately decreases the upper gate pulse width.
The PHASE waveform shows that upper gate is not turned
on for three to four cycles as the inductor sheds load. The
upper gate pulse width is then narrow for the next few cycles
as the inductor slowly picks up load current. The output
voltage quickly settles back to the +1.5V set point.
The leading edge transient response is less than 30µs and
the trailing edge transient response is less than 20µs.
Achieving a faster transient response time means reducing
the output inductance. The lower inductance would allow the
inductor current to transition faster as load current changes.
The main trade-off in speeding up transient response is a
drop in efficiency due to the reduced inductance.
Efficiency
The performance of the ISL6521EVAL1 board, loaded from
1A to 6A, is plotted in Figure 8. Measurements were taken at
70
95
90
85
80
75
FIGURE 7. TRAILING EDGE TRANSIENT RESPONSE
1
FIGURE 8. EFFICIENCY vs LOAD CURRENT
2
1.5V
OUTPUT CURRENT (A)
3
10µs/div
4
VOUT1, 50mV/div
PHASE, 5V/div
IOUT1, 5A/div
5
July 10, 2006
AN1247.0
6