ISL6521EVAL1Z Intersil, ISL6521EVAL1Z Datasheet - Page 4

• Manufacturer Part Number: ISL6521EVAL1Z
• Description: EVALUATION BOARD 1 ISL6521
• Manufacturer: Intersil

Specifications of ISL6521EVAL1Z

• Main Purpose: DC/DC, Step Down with LDO
• Outputs And Type: 4, Non-Isolated
• Voltage - Output: 1.5V, 2.5V, 3.3V, 1.8V
• Current - Output: 5A, 1A, 1A, 120mA
• Voltage - Input: 4.5 ~ 5.5V
• Regulator Topology: Buck
• Frequency - Switching: 300kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6521
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

room temperature at thermal equilibrium with no air flow. The
PWM converter design targets applications which specify a
minimum full load efficiency of 80%. Design modifications to
the output inductor and/or dual N-channel MOSFETs allow
for achieving higher efficiency.
Adapting Circuit Performance
The board outlined in this application note supports the use
of both surface mount and thru hole devices. This feature
adds flexibility to the evaluation process by allowing easy
replacement of components with counterparts for cost
versus performance curve balancing.
In surface mount only applications or designs with height
restrictions, the aluminum electrolytic bulk output capacitors
could be replaced with surface mount capacitors with similar
ESR characteristics and achieve similar performance. The
Sanyo SVPC series or Panasonic SP series capacitors
provide surface mount options over a range of price points.
Depending on the PWM output voltage ripple requirements,
inductor and output capacitor selection are critical in
achieving desired circuit performance. Care must be taken
to adjust the compensation components when changing
output capacitance and/or inductance.
Linear Combinations
The ISL6521 linear controllers can be used individually to
provide 120mA each or drive an external pass device to
achieve up to 3A. Two linear controllers can be ganged
together to create one 240mA regulator or all three linears
can be tied together to source 360mA. The ISL6521EVAL1
evaluation platform supports evaluation of this option. First,
the external pass devices, Q2 and Q3, must be removed.
The external pass devices, outlined in yellow, are highlighted
in Figure 9. Next, resistors options, outlined in green, must
be populated to short the output planes of each linear
together. The feedback resistor pairs, accented in red, for
each linear must be matching to provide proper voltage
feedback. The minimum current output, over temperature
and process variations, from the combined linears is 300mA.
FIGURE 9. COMPONENT CHANGES FOR COMBINING
LINEARS
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Application Note 1247
Layout Considerations
Component placement and trace layout is important in high
frequency switching converter design. With power devices
switching efficiently at 300kHz, the resulting current
transitions from one device to another cause voltage spikes
across the interconnecting impedances and parasitic circuit
elements. These voltage spikes can degrade efficiency,
radiate noise into the circuit, and lead to device over-voltage
stress. Careful component layout and printed circuit board
design minimizes these voltage spikes.
Component Placement
The switching components should be placed close to the
ISL6521 first. Minimize the length of the connections between
the input capacitors, C4 and C5, and the power switch, Q1, by
placing them nearby. Position both the ceramic and bulk input
capacitors as close to the upper MOSFET drain as possible.
Position the output inductor and output capacitors between
the upper and lower MOSFETs and the load.
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Place the PWM converter compensation
components close to the FB and COMP pins. The feedback
resistors should be located as close as possible to the FB
pin with vias tied straight to the ground plane as required.
Trace Routing and Interconnects
Keep the trace from the PHASE terminal to the output
inductor short and wide. A power plane layer, if available,
should support the input power and output power nodes.
Use copper filled polygons on the phase node layers. Keep
the traces from the UGATE and LGATE pins to the MOSFET
gates short and wide to easily handle the 1A of drive current.
In order to dissipate heat generated by the internal linears
and PWM drivers, the ground pads (pins 5 and 9) should be
connected to the ground plane through at least four vias.
This allows the heat to move away from the IC and also ties
the pad to the ground plane through a low impedance path.
Summary
The ISL6521EVAL1 is an adaptable evaluation tool which
showcases the performance of the ISL6521CB. Designed to
meet the performance requirements of current FPGA
applications, it allows the user the flexibility to configure it for
future designs as well. The following pages provide a
schematic of the board, bill of materials, and layout drawings
to support implementation of this solution.
References
Intersil documents are available on the web at
http://www.intersil.com/
[1] ISL6521 Data Sheet, Intersil Corporation, File No.
FN9148
July 10, 2006
AN1247.0