ISL6548A-6506EVAL1Z Intersil, ISL6548A-6506EVAL1Z Datasheet - Page 5

• Manufacturer Part Number: ISL6548A-6506EVAL1Z
• Description: EVALUATION BOARD ISL6548A-6506
• Manufacturer: Intersil

Specifications of ISL6548A-6506EVAL1Z

• Main Purpose: Special Purpose DC/DC, DDR Memory Supply
• Outputs And Type: 7, Non-Isolated
• Power - Output: 178W
• Voltage - Output: 1.8V, 3.3V, 5V, 1.5V, 1.2V, 2.5V, 0.9V
• Current - Output: 15A, 14A, 14A, 10A, 5A, 5A, 2A
• Voltage - Input: 3.3V, 5V, 12V
• Regulator Topology: Buck
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6506, ISL6548A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency - Switching: -

upper and lower MOSFETs was the Vishay Si7840BDP. The
choice of both the MOSFET and the parallel MOSFET
configuration will actually allow for a continuous current of at
least 20A without the FETs becoming too hot.
The transient specifications were met by employing large
value capacitors that have relatively low ESR ratings and by
using some ceramic capacitors to decrease the effective
ESR even more. Three 1800µF bulk capacitors with 16mΩ
ESR were utilized as the bulk output capacitance. During a
transient, the large capacitance supplies energy to the load
while the output inductor current slews up to match the load
current.
The output inductor was designed so that the ripple voltage
on the output rail would be approximately 20mV. A simple
wirewound toroidal inductor was designed for this regulator.
To save on the Bill of Material (BoM) cost, the same inductor
was used on the input filter to the V
Since there is an input inductor, the input capacitors must be
rated to handle all of the AC RMS current going through the
upper MOSFET. The capacitors that were chosen have RMS
current ratings that exceed the maximum RMS current
expected at full load.
The final aspect to the V
insure the stability of the system. A Type III compensation
network was chosen for this design. The compensation
components were calculated to give a system bandwidth of
about 50kHz with a Phase Margin of approximately 65°. For
more information on calculating the compensation
components for a single phase buck regulator, see Intersil’s
Technical Brief, TB417, titled “Designing Stable
Compensation Networks for Single Phase Voltage Mode
Buck Regulators.”[3]
V
The regulation of the V
converting from the 3.3VATX rail with a switching regulator.
The ISL6548A incorporates all the control aspects of the
switching regulator and requires that a MOSFET gate driver
be utilized to drive the upper and lower MOSFETs of the
synchronous buck switching regulator. This design utilizes
the ISL6613 to drive the switching MOSFETs. The
MOSFETs chosen were dual packaged FETs from Vishay,
the Si7844. The FETs and the package allow for efficient
regulation at full load of 10A. The output inductor is the same
as the input and output inductor used in the V
The output capacitor allows for a large amount of
capacitance while minimizing the output ripple to less than
40mV. The compensation network is a Type III. This network
yields a stable system with approximately 30kHz of
bandwidth.
GMCH
SWITCHING REGULATOR
GMCH
DDQ_DDR
rail is accomplished by down
5
regulator design was to
DDQ
regulator.
DDQ
Application Note 1285
regulator.
LDO REGULATORS
The V
control circuitry and pass element are incorporated within
the ISL6548A. Except for the pass element and output
capacitance, all other circuitry for the remaining LDOs is also
contained within the ISL6548A.
The V
internal LDO controllers. The pass elements chosen for both
was the Vishay Si7840BDP. This allowed for a higher single
part count on the BoM while allowing the regulators to
source a sufficient amount of load.
For all the LDOs, including the V
output capacitance was chosen to maintain a stable output
rail while minimizing voltage excursions due to load
transients.
GRANTSDALE VDAC SEQUENCING CIRCUITRY
The Grantsdale chipset imposes special requirements on the
startup and shutdown timing of the V
the V
up until the V
entering a sleep state, the V
the V
ramp down.
A circuit was included on the ISL6548A evaluation board
that will keep a 0.7V differential between the V
V
also discharge the V
a sleep state. This circuit is shown in Figure 7. During start-
up, the base-emitter junction of Q302 maintains a 0.7V
differential between V
the SLP_S3# signal, Q303 discharges the V
allows the V
DAC
FIGURE 7. GRANTSDALE SEQUENCING CIRCUITRY
GMCH
GMCH
TT_DDR
DAC
rails until the V
and V
rail. During start up, the V
rail level before the V
GMCH
GMCH
regulator required minimal design work as the
TT_GMCH/CPU
SLP_S3#
rail to discharge.
3V3ATX
VGMCH
rail has reached at least 0.7V. When
DAC
DAC
VDAC
GMCH
rail immediately upon entering into
rail is soft started. This circuit will
DAC
and V
are both regulated via the
TT_DDR
rail must be brought below
GMCH
Q303
DAC
Q302
DAC
DAC
. Upon assertion of
rail can begin to
regulator, the
rail in relation to
rail must not start
DAC
GMCH
January 15, 2007
rail which
and
AN1285.0