ISL6548A-6506EVAL1Z Intersil, ISL6548A-6506EVAL1Z Datasheet - Page 7

• Manufacturer Part Number: ISL6548A-6506EVAL1Z
• Description: EVALUATION BOARD ISL6548A-6506
• Manufacturer: Intersil

Specifications of ISL6548A-6506EVAL1Z

• Main Purpose: Special Purpose DC/DC, DDR Memory Supply
• Outputs And Type: 7, Non-Isolated
• Power - Output: 178W
• Voltage - Output: 1.8V, 3.3V, 5V, 1.5V, 1.2V, 2.5V, 0.9V
• Current - Output: 15A, 14A, 14A, 10A, 5A, 5A, 2A
• Voltage - Input: 3.3V, 5V, 12V
• Regulator Topology: Buck
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6506, ISL6548A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency - Switching: -

inductor current must slew up/down to supply the load
current while the linear regulator control will apply more
voltage to the gate of the pass FET.
Figure 12 shows V
The response of the V
brings the output voltage back into regulation very quickly.
The V
V
Figure 13 shows the V
transient load. Figure 14 shows the V
under a sourcing transient load.
GMCH
NOTE: ALL SIGNALS AT 50mV/DIV UNLESS OTHERWISE STATED
FIGURE 13. SOURCING TRANSIENT ON V
NOTE: ALL SIGNALS AT 50mV/DIV UNLESS OTHERWISE STATED
TT_GMCH/CPU
rail since it is derived from the V
FIGURE 12. TRANSIENT ON V
V
V
TT_GMCH/CPU
TT_GMCH/CPU
GMCH
V
V
DDQ_DDR
DDQ_DDR
V
V
V
V
GMCH
rail is affected by the transient on the
DAC
GMCH
DAC
V
V
GMCH
TT_GMCH/CPU
TIMEBASE: 200µs/DIV
TIMEBASE: 200µs/DIV
TT
TT
(2.5V OFFSET)
under transient loading.
(2.5V OFFSET)
(0.9V OFFSET)
(0.9V OFFSET)
1A/DIV
1A/DIV
I
I
(1.5V OFFSET)
(1.5V OFFSET)
LOAD
LOAD
(1.8V OFFSET)
(1.8V OFFSET)
regulator to the transient load
(1.2V OFFSET)
7
(1.2V OFFSET)
TT_GMCH/CPU
rail under a sourcing
GMCH
GMCH
TT_GMCH/CPU
rail.
Application Note 1285
rail
The loading of this rail is light enough such that the response
of the V
Figure 15 shows the V
Fault Protection
Figures 16, 17, 18, 19 and 20 show the response of the
system to a shorts on the V
rail, V
NOTE: ALL SIGNALS AT 50mV/DIV UNLESS OTHERWISE STATED
NOTE: ALL SIGNALS AT 50mV/DIV UNLESS OTHERWISE STATED
FIGURE 14. SINKING TRANSIENT ON V
TT_GMCH/CPU
GMCH
FIGURE 15. TRANSIENT ON V
rail is negligible.
V
V
TT_GMCH/CPU
TT_GMCH/CPU
V
V
DDQ_DDR
V
V
DDQ_DDR
V
V
rail and V
GMCH
DAC
GMCH
V
DAC
DAC
TIMEBASE: 200µs/DIV
V
TIMEBASE: 200µs/DIV
TT
TT
(2.5V OFFSET)
(0.9V OFFSET)
1A/DIV
(2.5V OFFSET)
I
(0.9V OFFSET)
(1.5V OFFSET)
LOAD
(1.5V OFFSET)
1A/DIV
I
rail under transient loading.
DDQ_DDR
LOAD
(1.8V OFFSET)
(1.8V OFFSET)
(1.2V OFFSET)
(1.2V OFFSET)
DAC
rail, respectively.
rail, V
TT_GMCH/CPU
DAC
TT
, rail, V
January 15, 2007
GMCH
AN1285.0