ISL6559EVAL1 Intersil, ISL6559EVAL1 Datasheet - Page 4

• Manufacturer Part Number: ISL6559EVAL1
• Description: EVALUATION BOARD ISL6559
• Manufacturer: Intersil

Specifications of ISL6559EVAL1

• Main Purpose: Special Purpose DC/DC, VRM Supply
• Outputs And Type: 1, Non-Isolated
• Power - Output: 125W
• Voltage - Output: 1.25V
• Current - Output: 100A
• Voltage - Input: 5V, 12V
• Regulator Topology: Buck
• Frequency - Switching: 600kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6559, ISL6605
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

1.0V
Overcurrent Protection
The ISL6559 monitors the output current level by averaging
the sampled current from each ISEN pin. The R
resistors (R1, R2, R3, R4) are selected such that the current
sourced by the ISEN pins is 50µA at maximum load current.
The average of the sampled currents is compared with an
overcurrent trip level of 90µA. Once the average current
meets or exceeds the OC reference current, the controller
immediately places all PWM signals in a high-impedance
state, quickly removing gate drive to the ISL6605 drivers.
This forces the core voltage to decay as the output
capacitors discharge. The PGOOD signal transitions low
when the core voltage drops below the UV threshold.
After the overcurrent event is detected, the controller waits a
short delay time before initiating a soft-start interval to allow
the disturbance to clear. The delay time is equivalent to the
soft-start interval and for this design is 3.4ms. If during the
soft-start interval another overcurrent trip is detected, the
PWM signals are again placed in a high impedance state
and PGOOD remains low. The controller waits another
3.4ms before another soft-start interval is attempted. This
hiccup mode of operation repeats up to six times, with a
seventh successive event causing the converter to latch off.
Figure 5 shows the hiccup mode operation of the converter
when a hard short is applied across the output terminals of
the evaluation board. The converter quickly places the PWM
signals in a high-impedance state and the core voltage
decays quickly. The short is not removed, resulting in the
controller latching off after the seventh attempt. The hiccup
mode is explained more thoroughly in the datasheet.
0A
0V
0V
0V
FIGURE 5. OVERCURRENT PROTECTION
LOAD CURRENT, 20A/DIV
PWM3, 10V/DIV
PWM1, 10V/DIV
PWM2, 10V/DIV
VCORE, 1V/DIV
10ms/DIV
4
ISEN
Application Note 1132
VID on the Fly
The AMD Hammer Family microprocessors can change VID
inputs at any time while the regulator is in operation. The
power management solution is required to monitor the DAC
inputs and respond to VID voltage transitions in a controlled
manner, supervising the safe output voltage transition within
the DAC range of the processor without discontinuity or
disruption. The ISL6559 checks the five VID inputs at the
beginning of each switching cycle. If the VID code has
changed, the controller waits one complete switching cycle
to validate the new code. If the new code is stable during this
one cycle delay, then the controller begins incrementing the
reference voltage toward the new DAC code in 25mV steps,
every two switching-cycles, until the new DAC code is
reached.
Figure 6 shows a 250mV DAC change prompted by
changing VID3 and VID1 simultaneously. Originally at
1.550V (00000), the core voltage ramps to the new DAC
setting of 1.300V (01010). The VID-on-the-Fly transition is
completed in 30µs, well within the 100µs maximum window
allowed. The converter is supporting a 26A load during the
transition. The cursors on the scope shot reflect only a
230mV transition because the transition happened very fast
and the final voltage was not captured.
Figure 7 shows the converter returning to a DAC level of
1.550V after the VID3 and VID1 states are returned to
ground. Again, the converter is loaded at 26A during the
DAC change.
FIGURE 6. VID-ON-THE-FLY TRANSITION FROM 1.55V TO
1.30V