CDB4351 Cirrus Logic Inc, CDB4351 Datasheet - Page 16

• Manufacturer Part Number: CDB4351
• Description: BOARD EVAL FOR CS4351 DAC
• Manufacturer: Cirrus Logic Inc
• Series: Popguard®r

Specifications of CDB4351

• Number Of Dac's: 2
• Number Of Bits: 24
• Outputs And Type: 1, Single Ended
• Sampling Rate (per Second): 192k
• Data Interface: Serial
• Dac Type: Voltage
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Utilized Ic / Part: CS4351
• Description/function: Audio D/A
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: CS4351
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1152

16
4.3
4.3.1
4.3.2
Digital Interface Format
The device will accept audio samples in 1 of 4 digital interface formats in Stand-Alone mode, as illustrated
in
The desired format is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship
between the LRCK, SCLK and SDIN, see
edge of SCLK. Also, SCLK must have at least 32 cycles per LRCK period in format 2, and 48 cycles per
LRCK period in format 3.
Sample Rate
Sample Rate
Sample Rate
Stand-Alone Mode
The desired format is selected via the DIF2, DIF1 and DIF0 bits in the Mode Control 2 register (see section
Section
Figures 5
Table
Control Port Mode
(kHz)
(kHz)
(kHz)
176.4
44.1
88.2
192
48
32
64
96
6, and 1 of 6 formats in Control Port mode, as illustrated in
6.2.1). For an illustration of the required relationship between LRCK, SCLK and SDIN, see
through 7. For all formats, SDIN is valid on the rising edge of SCLK. Also, SCLK must have at
DIF0 DIF1
0
0
1
1
11.2896
12.2880
8.1920
256x
0
1
0
1
12.2880
11.2896
Table 6. Digital Interface Format - Stand-Alone Mode
12.2880
11.2896
Table 4. Double-Speed Mode Standard Frequencies
8.1920
Table 3. Single-Speed Mode Standard Frequencies
128x
Table 5. Quad-Speed Mode Standard Frequencies
64x
I
Left Justified, up to 24-bit Data
Right Justified, 24-bit Data
Right Justified, 16-bit Data
2
= Denotes clock modes which are NOT auto detected
S, up to 24-bit Data
12.2880
16.9344
18.4320
384x
DESCRIPTION
12.2880
16.9344
18.4320
16.9344
18.4320
192x
96x
Figures 5
16.3840
22.5792
24.5760
512x
through 7. For all formats, SDIN is valid on the rising
MCLK (MHz)
MCLK (MHz)
MCLK (MHz)
16.3840
22.5792
24.5760
22.5792
24.5760
256x
128x
24.5760
33.8688
36.8640
FORMAT
768x
0
1
2
3
Table
24.5760
33.8688
36.8640
33.8688
36.8640
384x
7.
192x
FIGURE
32.7680
45.1584
49.1520
1024x
6
5
7
7
45.1584
49.1520
32.7680
45.1584
49.1520
512x
256x
36.8640
1152x
CS4351
DS566F1