EVAL-AD5429EBZ Analog Devices Inc, EVAL-AD5429EBZ Datasheet - Page 22

• Manufacturer Part Number: EVAL-AD5429EBZ
• Description: BOARD EVALUATION FOR AD5429
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5429EBZ

• Number Of Dac's: 2
• Number Of Bits: 8
• Outputs And Type: 2, Single Ended
• Sampling Rate (per Second): 2.47M
• Data Interface: Serial
• Settling Time: 30ns
• Dac Type: Current
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 125°C
• Utilized Ic / Part: AD5429
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5429/AD5439/AD5449
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD54xx family of DACs is
through a serial bus that uses standard protocol and is compatible
with microcontrollers and DSP processors. The communication
channel is a 3-wire interface consisting of a clock signal, a data
signal, and a synchronization signal. The AD5429/AD5439/
AD5449 require a 16-bit word, with the default being data valid
on the falling edge of SCLK; however, this is changeable using
the control bits in the data-word.
ADSP-21xx-to-AD5429/AD5439/AD5449 Interface
The ADSP-21xx family of DSPs is easily interfaced to an AD5429/
AD5439/AD5449 DAC without the need for extra glue logic.
Figure 48 is an example of a serial peripheral interface (SPI)
between the DAC and the ADSP-2191. The MOSI (master output,
slave input) pin of the DSP drives the serial data line, SDIN.
SYNC is driven from a port line, in this case SPIxSEL .
The ADSP-2101/ADSP-2103/ADSP-2191 processor incorporates
channel synchronous serial ports (SPORT). A serial interface
between the DAC and DSP SPORT is shown in Figure 49. In this
interface example, SPORT0 is used to transfer data to the DAC
shift register. Transmission is initiated by writing a word to the Tx
register after SPORT has been enabled. In a write sequence, data
is clocked out on each rising edge of the DSP serial clock and
clocked into the DAC input shift register on the falling edge of
its SCLK. Updating of the DAC output takes place on the rising
edge of the SYNC signal.
Communication between two devices at a given clock speed is
possible when the following specifications are compatible: frame
SYNC delay and frame SYNC setup-and-hold, data delay and
data setup-and-hold, and SCLK width. The DAC interface expects
a t
minimum.
*ADDITIONAL PINS OMITTED FOR CLARITY.
*ADDITIONAL PINS OMITTED FOR CLARITY.
ADSP-2101/
ADSP-2103/
ADSP-2191
4
( SYNC falling edge to SCLK falling edge setup time) of 13 ns
ADSP-2191*
Figure 48. ADSP-2191 SPI-to-AD5429/AD5439/AD5449 Interface
Figure 49. ADSP-2101/ADSP-2103/ADSP-2191 SPORT-to-
*
SPIxSEL
SCLK
MOSI
SCK
TFS
DT
AD5429/AD5439/AD5449 Interface
SYNC
SDIN
SCLK
AD5429/AD5439/
SYNC
SDIN
SCLK
AD5429/AD5439/
AD5449
AD5449*
*
Rev. C | Page 22 of 32
See the ADSP-21xx user manual at
on clock and frame SYNC frequencies for the SPORT register.
Table 12
Table 12. SPORT Control Register Setup
Name
TFSW
INVTFS
DTYPE
ISCLK
TFSR
ITFS
SLEN
ADSP-BF5xx-to-AD5429/AD5439/AD5449 Interface
The ADSP-BF5xx family of processors has an SPI-compatible port
that enables the processor to communicate with SPI-compatible
devices. A serial interface between the BlackFin ® processor and
the AD5429/AD5439/AD5449 DAC is shown in Figure 50. In
this configuration, data is transferred through the MOSI pin.
SYNC is driven by the SPIxSEL pin, which is a reconfigured
programmable flag pin.
A serial interface between the DAC and the DSP SPORT is shown
in Figure 51. When SPORT is enabled, initiate transmission by
writing a word to the Tx register. The data is clocked out on each
rising edge of the DSP serial clock and clocked into the DAC
input shift register on the falling edge of its SCLK. The DAC
output is updated by using the transmit frame synchronization
(TFS) line to provide a SYNC signal.
*ADDITIONAL PINS OMITTED FOR CLARITY.
*ADDITIONAL PINS OMITTED FOR CLARITY.
ADSP-BF5xx*
ADSP-BF5xx*
Figure 51. ADSP-BF5xx SPORT-to-AD5429/AD5439/AD5449 Interface
Figure 50. ADSP-BF5xx-to-AD5429/AD5439/AD5449 Interface
shows the setup for the SPORT control register.
SPIxSEL
Setting
1
1
00
1
1
1
1111
SCLK
MOSI
SCK
TFS
DT
Description
Alternate framing
Active low frame signal
Right-justify data
Internal serial clock
Frame every word
Internal framing signal
16-bit data-word
www.analog.com
SYNC
SDIN
SCLK
AD5429/AD5439/
SYNC
SDIN
SCLK
AD5429/AD5439/
AD5449*
AD5449*
for details