EVAL-AD5429EBZ Analog Devices Inc, EVAL-AD5429EBZ Datasheet - Page 5

• Manufacturer Part Number: EVAL-AD5429EBZ
• Description: BOARD EVALUATION FOR AD5429
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5429EBZ

• Number Of Dac's: 2
• Number Of Bits: 8
• Outputs And Type: 2, Single Ended
• Sampling Rate (per Second): 2.47M
• Data Interface: Serial
• Settling Time: 30ns
• Dac Type: Current
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 125°C
• Utilized Ic / Part: AD5429
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
All input signals are specified with t
V
Table 2.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Update Rate
1
2
3
TIMING DIAGRAMS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Guaranteed by design and characterization, not subject to production test.
Falling or rising edge as determined by the control bits of the serial word. Strong or weak SDO driver selected via the control register.
Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications are measured with a load circuit, as shown in Figure 5.
REF
3
= 10 V, I
1
OUT
LDAC
LDAC
1
2
NOTES
1. ALTERNATIVELY, DATA CAN BE CLOCKED INTO THE INPUT SHIFT REGISTER ON THE RISING EDGE OF SCLK AS
SYNC
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
SCLK
SDIN
2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications T
DETERMINED BY THE CONTROL BITS. TIMING IS AS ABOVE, WITH SCLK INVERTED.
Limit at T
50
20
8
8
13
5
4
5
30
0
12
10
25
60
12
4.5
2.47
1
2
MIN
t
8
, T
MAX
t
4
DB15
R
= t
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
MSPS
F
t
= 1 ns (10% to 90% of V
5
t
6
Figure 2. Standalone Mode Timing Diagram
Conditions/Comments
Maximum clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Data setup time
Data hold time
SYNC rising edge to SCLK falling edge
Minimum SYNC high time
SCLK falling edge to LDAC falling edge
LDAC pulse width
SCLK falling edge to LDAC rising edge
SCLK active edge to SDO valid, strong SDO driver
SCLK active edge to SDO valid, weak SDO driver
CLR pulse width
SYNC rising edge to LDAC falling edge
Consists of cycle time, SYNC high time, data setup, and output voltage settling time
t
2
Rev. C | Page 5 of 32
t
1
DD
t
3
) and timed from a voltage level of (V
DB0
t
7
t
9
2
t
10
t
11
MIN
to T
AD5429/AD5439/AD5449
MAX
IL
, unless otherwise noted.
+ V
IH
)/2. V
DD
= 2.5 V to 5.5 V,