CDB4392 Cirrus Logic Inc, CDB4392 Datasheet - Page 16

• Manufacturer Part Number: CDB4392
• Description: EVALUATION BOARD FOR CS4392
• Manufacturer: Cirrus Logic Inc

Specifications of CDB4392

• Number Of Dac's: 2
• Number Of Bits: 24
• Outputs And Type: 2, Differential
• Sampling Rate (per Second): 192k
• Data Interface: Serial
• Dac Type: Voltage
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Utilized Ic / Part: CS4392
• Description/function: Audio D/A
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: CS4392
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

4.1
16
4.1.1
4.1.2
INCR
7
0
4.0.3
In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock,
CCLK (see Figure 9 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip
select signal and is used to control SPI writes to the control port. When the device detects a high to
low transition on the AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs
and data is clocked in on the rising edge of CCLK.
Memory Address Pointer (MAP)
INCR (AUTO MAP INCREMENT ENABLE)
MAP3-0 (MEMORY ADDRESS POINTER)
Default = ‘0’
0 - Disabled,
1 - Enabled,
writes of successive registers
Default = ‘0000’
4.0.3a
To write to the device, follow the procedure below while adhering to the control port
Switching Specifications in section 7.
1) Bring CS low.
2) The address byte on the CDIN pin must then be 00100000.
3) Write to the memory address pointer, MAP. This byte points to the register to be written.
4) Write the desired data to the register pointed to by the MAP.
5) If the INCR bit (see section 4.0.1) is set to 1, repeat the previous step until all the desired
registers are written, then bring CS high.
6) If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is nec-
essary to bring CS high, and follow the procedure detailed from step 1. If no further writes
to other registers are desired, bring CS high.
Reserved
SPI Mode
6
0
the MAP will auto increment after each byte is written, allowing block reads or
the MAP will stay constant for successive writes
SPI Write
Reserved
C C L K
CS
C D IN
5
0
Figure 9. Control Port Timing, SPI mode
M A P = M em ory Ad dress P oin te r
ADDRESS
0 0 1 0 0 0 0
C H IP
Reserved
4
0
R/W
MAP3
M A P
3
0
MSB
byte 1
DATA
MAP2
byte n
2
0
L S B
MAP1
1
0
CS4392
DS459PP3
MAP0
0
0