CDB4392 Cirrus Logic Inc, CDB4392 Datasheet - Page 23

• Manufacturer Part Number: CDB4392
• Description: EVALUATION BOARD FOR CS4392
• Manufacturer: Cirrus Logic Inc

Specifications of CDB4392

• Number Of Dac's: 2
• Number Of Bits: 24
• Outputs And Type: 2, Differential
• Sampling Rate (per Second): 192k
• Data Interface: Serial
• Dac Type: Voltage
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Utilized Ic / Part: CS4392
• Description/function: Audio D/A
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: CS4392
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.6
6.6.1
DS459PP3
Reserved
B7
Mode Control 3 - Address 06h
Function:
Function:
Function:
Function:
Function:
Function:
Control Port Enable (Bit 5)
Power Down (Bit 4)
AMUTEC = BMUTEC (Bit 3)
Freeze (Bit 2)
Master Clock Divide (Bit 1)
Interpolation Filter Select (Bit 4)
This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode
can be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by
the registers and the pin definitions will conform to Control Port Mode. To accomplish a clean power-
up, the user should write 30h to register 5 within 10 ms following the release of Reset.
The device will enter a low-power state whenever this function is activated (set to 1). The power-down
bit defaults to ‘enabled’ (1) on power-up and must be disabled before normal operation will begin. The
contents of the control registers are retained when the device is in power-down.
When this function is enabled, the individual controls for AMUTEC and BMUTEC are internally con-
nected through a AND gate prior to the output pins. Therefore, the external AMUTEC and BMUTEC
pins will go active only when the requirements for both AMUTEC and BMUTEC are valid.
This function allows modifications to the control port registers without the changes taking effect until
Freeze is disabled. To make multiple changes in the Control port registers take effect simultaneously,
set the Freeze Bit, make all register changes, then Disable the Freeze bit.
This function allows the user to select an internal divide by 2 of the Master Clock. This selection is
required to access the higher Master Clock rates as shown in Tables 2 through 4 on page 10.
This Function allows the user to select whether the Interpolation Filter has a fast (set to 0 - default) or
slow (set to 1) roll off. The - 3dB corner is approximately the same for both filters, but the slope of
the roll of is greater for the ‘fast’ roll off filter.
Reserved
B6
Reserved
B5
FILT_SEL
B4
RMP_UP
B3
RMP_DN
B2
Reserved
B1
CS4392
Reserved
B0
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