EVALED7706 STMicroelectronics, EVALED7706 Datasheet - Page 16

• Manufacturer Part Number: EVALED7706
• Description: EVALUATION BOARD FOR LED7706
• Manufacturer: STMicroelectronics

Specifications of EVALED7706

• Current - Output / Channel: 30mA
• Outputs And Type: 6, Non-Isolated
• Voltage - Output: 36 V
• Features: Dimmable, Extra 5V Output
• Voltage - Input: 4.5 ~ 36 V
• Utilized Ic / Part: LED7706
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-6445

Operation description
5.1.6
16/46
Keeping the FSW pin voltage lower than 270 mV for more than 4.8 µs results in a stop of the
device switching activity. Normal operation is resumed as soon as FSW rises above the
mentioned threshold and the soft-start sequence is repeated.
The SYNC pin is a synchronization output and provides a 35 % (typ.) duty-cycle clock when
the LED7706 is used as master or a replica of the FSW pin when used as slave. It is used to
connect multiple devices in a daisy-chain configuration or to synchronize other switching
converters running in the system with the LED7706 (master operation). When an external
synchronization clock is applied to the FSW pin, the internal oscillator is over-driven: each
switching cycle begins at the rising edge of the clock, while the slope compensation
(
harmonic instability (see
have a 40 % maximum duty-cycle when the boost converter is working in continuous-
conduction mode (CCM) in order to assure that the slope compensation is effective (starts
with duty-cycle lower than 40%)
Figure 11. External sync waveforms
Slope compensation
The constant frequency, peak current-mode topology has the advantage of very easy loop
compensation with output ceramic caps (reduced cost and size of the application) and fast
transient response. In addition, the intrinsic peak-current measurement simplifies the
current limit protection, avoiding undesired saturation of the inductor.
On the other side, this topology has a drawback: there is an inherent open loop instability
when operating with a duty-ratio greater than 0.5. This phenomenon is known as “Sub-
Harmonic Instability” and can be avoided by adding an external ramp to the one coming
from the sensed current. This compensating technique, based on the additional ramp, is
called “slope compensation”. In
the small perturbation ΔI
and the system reverts to a stable situation.
Figure 11
Slave SYNC pin voltage
Slave LX pin voltage
FSW pin voltage (ext. sync)
) ramp starts at the falling edge of the same signal. Thus, to prevent sub-
L
Section 5.1.6
dies away in subsequent cycles thanks to the slope compensation
Figure 12
270mV threshold
), the external synchronization clock is required to
, where the switching duty-cycle is higher than 0.5,
270ns minimum
LED7706
AM00604v1