ADIS16251/PCBZ Analog Devices Inc, ADIS16251/PCBZ Datasheet - Page 5

• Manufacturer Part Number: ADIS16251/PCBZ
• Description: BOARD EVALUATION FOR ADIS16251
• Manufacturer: Analog Devices Inc
• Series: iMEMS®, iSensor™r

Specifications of ADIS16251/PCBZ

• Sensor Type: Gyroscope, 1 Axis
• Sensing Range: ±20°/sec, ±40°/sec, ±80°/sec
• Interface: SPI Serial
• Sensitivity: 0.004°/sec/LSB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Embedded: No
• Utilized Ic / Part: ADIS16251
• Silicon Manufacturer: Analog Devices
• Application Sub Type: Angular Rate Sensor / Gyroscope
• Kit Application Type: Sensing - Motion / Vibration / Shock
• Silicon Core Number: ADIS16251
• Kit Contents: Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADISUSBZ - KIT EVAL ADIS W/SOFTWARE USBADISEVALZ - KIT PC EVALUATION W/SOFTWARE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING SPECIFICATIONS
Table 2.
Parameter
f
t
t
t
t
t
t
t
t
t
t
1
2
3
SCLK
DATARATE
DATASTALL
CSHIGH
CS
DAV
DSU
DHD
DF
DR
SFS
Guaranteed by design; typical specifications are not tested or guaranteed.
The MSB presents an exception to this parameter. The MSB clocks out on the falling edge of CS . The rest of the DOUT bits are clocked out after the falling edge of SCLK
and are governed by this specification.
This parameter may need to be expanded to allow for proper capture of the LSB. After CS goes high, the DOUT line goes into a high impedance state.
DOUT
SCLK
DIN
CS
*NOT DEFINED
Description
Fast mode (SMPL_PRD ≥ 0x07; f
Normal mode (SMPL_PRD < 0x07; f
Data rate period, fast mode (SMPL_PRD ≥ 0x07; f
Data rate period, normal mode (SMPL_PRD < 0x07; f
Data stall time, fast mode (SMPL_PRD ≥ 0x07; f
Data stall time, normal mode (SMPL_PRD < 0x07; f
Chip select high
Chip select to clock edge
Data output valid after SCLK edge
Data input setup time before SCLK rising edge
Data input hold time after SCLK rising edge
Data output fall time
Data output rise time
CS high after SCLK edge
Flash update time (power supply must be within range)
t
CS
*
SCLK
1
CS
MSB
W/R
2
(Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)
DB14
t
3
DAV
t
DSU
3
S
A5
DB13
≥ 64 Hz)
2
S
≤ 56.9 Hz)
Figure 2. SPI Chip Select Timing
4
t
DHD
A4
DB12
t
Figure 3. SPI Timing
Rev. A | Page 5 of 5
DATARATE
t
S
DATASTALL
≥ 64 Hz)
5
S
≥ 64 Hz)
S
A3
≤ 56.9 Hz)
DB11
S
≤ 56.9 Hz)
6
A2
DB10
Min
0.01
0.01
32
42
9
12
1/f
48.8
24.4
48.8
5
50
D2
SCLK
DB2
1
15
D1
DB1
Typ
5
5
16
LSB
LSB
Max
2.5
1.0
100
12.5
12.5
t
SFS
ADIS16251
1
Unit
MHz
MHz
μs
μs
μs
μs
ns
ns
ns
ns
ns min
ns min
ns
ms