ATTINY20-EK1 Atmel, ATTINY20-EK1 Datasheet - Page 119
ATTINY20-EK1
Manufacturer Part Number
ATTINY20-EK1
Description
KIT EVAL TOUCH ATTINY20
Manufacturer
Atmel
Datasheet
1.ATTINY20-EK1.pdf
(224 pages)
Specifications of ATTINY20-EK1
Sensor Type
*
Sensing Range
*
Interface
*
Sensitivity
*
Voltage - Supply
*
Embedded
*
Utilized Ic / Part
*
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
TinyAVR
Kit Contents
Board
Svhc
No SVHC (15-Dec-2010)
Mcu Supported Families
ATtiny20
Tool / Board Applications
Microcontroller
Rohs Compliant
Yes
Tool Type
Development Kit
Cpu Core
AVR 8
Data Bus Width
8 bit
Processor To Be Evaluated
ATtiny20
Interface Type
Touch
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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15.6.2
15.7
15.8
8235B–AVR–04/11
ADC Noise Canceler
Analog Input Circuitry
ADC Voltage Reference
The ADC reference voltage (V
channels that exceed V
V
gap reference (V
The first ADC conversion result after switching reference voltage source may be inaccurate, and
the user is advised to discard this result.
The ADC features a noise canceler that enables conversion during sleep mode. This reduces
noise induced from the CPU core and other I/O peripherals. The noise canceler can be used
with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure
should be used:
Note that the ADC will not automatically be turned off when entering other sleep modes than Idle
mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before enter-
ing such sleep modes to avoid excessive power consumption.
The analog input circuitry for single ended channels is illustrated in
source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regard-
less of whether that channel is selected as input for the ADC. When the channel is selected, the
source must drive the S/H capacitor through the series resistance (combined resistance in the
input path).
The ADC is optimized for analog signals with an output impedance of approximately 10kΩ or
less. If such a source is used, the sampling time will be negligible. If a source with higher imped-
ance is used, the sampling time will depend on how long time the source needs to charge the
S/H capacitor, which can vary widely. The user is recommended to only use low impedance
sources with slowly varying signals, since this minimizes the required charge transfer to the S/H
capacitor.
CC
• Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must
• Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the
• If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake
channel selection. Since the next conversion has already started automatically, the next
result will reflect the previous channel selection. Subsequent conversions will reflect the new
channel selection.
be selected and the ADC conversion complete interrupt must be enabled.
CPU has been halted.
up the CPU and execute the ADC Conversion Complete interrupt routine. If another interrupt
wakes up the CPU before the ADC conversion is complete, that interrupt will be executed,
and an ADC Conversion Complete interrupt request will be generated when the ADC
conversion completes. The CPU will remain in active mode until a new sleep command is
executed.
, or internal 1.1V reference. The internal 1.1V reference is generated from the internal band-
BG
) through an internal amplifier.
REF
will result in codes close to 0x3FF. V
REF
) indicates the conversion range for the ADC. Single ended
REF
can be selected as either
Figure
ATtiny20
15-8. An analog
119
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