DV164136 Microchip Technology, DV164136 Datasheet

DEVELOPMENT KIT FOR PIC18

DV164136

Manufacturer Part Number
DV164136
Description
DEVELOPMENT KIT FOR PIC18
Manufacturer
Microchip Technology
Series
PIC®r
Type
MCUr
Datasheets

Specifications of DV164136

Contents
Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
Processor To Be Evaluated
PIC18F8722, PIC18F87J11
Interface Type
RS-232, USB
Operating Supply Voltage
3.3 V, 5 V
Silicon Manufacturer
Microchip
Core Architecture
PIC
Core Sub-architecture
PIC18
Silicon Core Number
PIC18F
Silicon Family Name
PIC18F8xxx
Kit Contents
PIC18 Exp Brd PICkit 3 Cable CD PSU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
PIC18F8722, PIC18F87J11
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DV164136
Manufacturer:
MICROCHIP
Quantity:
12 000
The PIC18F6627/6722/8627/8722 Rev. B1 parts you
have received conform functionally to the Device Data
Sheet
described below. Any Data Sheet Clarification issues
related to the PIC18F6627/6722/8627/8722 will be
reported in a separate Data Sheet errata. Please check
the Microchip web site for any existing issues.
The
PIC18F6627/6722/8627/8722 devices with these
Device/Revision IDs:
All of the issues listed here will be addressed in future
revisions of the PIC18F6627/6722/8627/8722 silicon.
1. Module: Master Synchronous Serial Port
© 2009 Microchip Technology Inc.
The Device IDs (DEVID1 and DEVID2) are located at
addresses
configuration space. They are shown in binary in the
format “DEVID2 DEVID1”.
Part Number
PIC18F6627
PIC18F6722
PIC18F8627
PIC18F8722
In SPI mode, the Buffer Full flag (BF bit in the
SSPxSTAT register), the Write Collision Detect bit
(WCOL in SSPxCON1) and the Receive Overflow
Indicator bit (SSPOV in SSPxCON1) are not reset
upon disabling the SPI module (by clearing the
SSPEN bit in the SSPxCON1 register).
For example, if SSPxBUF is full (BF bit is set), and
the MSSP module is disabled and re-enabled, the
BF bit will remain set. In SPI Slave mode, a sub-
sequent write to SSPxBUF will result in a write
collision. Also, if a new byte is received, a receive
overflow will occur.
Work around
Ensure that if the buffer is full, SSPxBUF is read
(thus clearing the BF flag) and WCOL is clear
before disabling the MSSP module. If the module
is configured in SPI Slave mode, ensure that the
SSPOV bit is clear before disabling the module.
Date Codes that pertain to this issue:
All engineering and production devices.
following
(DS39646C),
PIC18F6627/6722/8627/8722 Rev. B1 Silicon Errata
3FFFFEh:3FFFFFh
(MSSP) — Serial Peripheral
Interface (SPI)
silicon
0001 0100 000
0001 0100 001
0001 0011 110
0001 0011 111
Device ID
except
errata apply
for
in
the
PIC18F6627/6722/8627/8722
Revision ID
the
0 0010
0 0010
0 0010
0 0010
anomalies
only
device’s
to
2. Module: Capture/Compare/PWM (CCP)
3. Module: MSSP (I
PWM output of 10-bit resolution is not available for
either CCP4 or CCP5 when Timer4 is being used
as the PWM time base (T3CON<6,3> = 01, 10 or
11) for the PWM mode (CCPxCON<3:2> = 11).
Work around
For 10-bit resolution, use Timer2 as the PWM time
base (T3CON<6,3> = 00).
For 8-bit resolution, use Timer4 or Timer2 as the
PWM time base and set the two LSBs to ‘00’
(CCPxCON<5:4> = 00).
Date Codes that pertain to this issue:
All engineering and production devices.
In extremely rare cases, when configured for I
slave reception, the MSSP module may not receive
the correct data. This occurs only if the Serial
Receive/Transmit Buffer Register (SSPxBUF) is not
read within a window after the SSPxIF interrupt has
occurred.
For SSP1BUF, the flag bit is SSP1IF (PIR1<3>).
For SSP2BUF, the flag bit is SSP2IF (PIR3<7>).
Work around
The issue can be resolved in either of these ways:
• Prior to the I
• Each time the SSPxIF bit is set, read the
Date Codes that pertain to this issue:
All engineering and production devices.
clock-stretching feature.
This
(SSP1CON2<0>).
SSPxBUF before the first rising clock edge of
the next byte being received.
is
done
2
C slave reception, enable the
2
by
C™ Slave)
setting
DS80343B-page 1
the
SEN
2
C™
bit

Related parts for DV164136

DV164136 Summary of contents

Page 1

... SPI Slave mode, ensure that the SSPOV bit is clear before disabling the module. Date Codes that pertain to this issue: All engineering and production devices. © 2009 Microchip Technology Inc. PIC18F6627/6722/8627/8722 2. Module: Capture/Compare/PWM (CCP) PWM output of 10-bit resolution is not available for ...

Page 2

... Timer 1 with 0xFFFF, the Timer1 interrupt will not get set on the first overflow from 0xFFFF to 0x0000. All subsequent overflows, from 0xFFFF to 0x0000, will work correctly. Work around None. Date Codes that pertain to this issue: All engineering and production devices. © 2009 Microchip Technology Inc. ...

Page 3

... REVISION HISTORY Rev A Document (8/2007) Initial release of this errata. Includes silicon issues 1 (MSSP) and 2 (CCP). Rev B Document (2/2009) 2 Added silicon issues 3 (MSSP – Slave), 4 (MSSP – Master), 5 (Enhanced Universal Synchronous Asynchronous – EUSART) and 6 (Timer1). © 2009 Microchip Technology Inc. PIC18F6627/6722/8627/8722 DS80343B-page 3 ...

Page 4

... PIC18F6627/6722/8627/8722 NOTES: DS80343B-page 4 © 2009 Microchip Technology Inc. ...

Page 5

... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 6

... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2009 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...

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