DV164136 Microchip Technology, DV164136 Datasheet
DV164136
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... Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology © 2008 Microchip Technology Inc. PIC18F8722 Family Data Sheet 64/80-Pin, 1-Mbit, DS39646C ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F8722 128K 65536 3936 © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Peripheral Highlights (Continued): • Capture/Compare/PWM (CCP) modules, one with Auto-Shutdown (28-pin devices) • Master Synchronous Serial Port (MSSP) module Supporting 3-Wire SPI (all 4 modes) and I Master and Slave modes • ...
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... RF5/AN10/CV REF 13 RF4/AN9 14 RF3/AN8 15 RF2/AN7/C1OUT Note 1: The ECCP2/P2A pin placement is determined by the CCP2MX Configuration bit. DS39646C-page PIC18F6527 42 PIC18F6622 41 PIC18F6627 40 PIC18F6722 RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3 RB4/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC V SS OSC2/CLKO/RA6 OSC1/CLKI/RA7 V DD RB7/KBI3/PGD RC5/SDO1 RC4/SDI1/SDA1 RC3/SCK1/SCL1 RC2/ECCP1/P1A © 2008 Microchip Technology Inc. ...
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... RF3/AN8 17 RF2/AN7/C1OUT 18 (2) RH7/AN15/P1B 19 (2) RH6/AN14/P1C Note 1: The ECCP2/P2A pin placement is determined by the CCP2MX Configuration bit and Processor mode settings. 2: P1B, P1C, P3B and P3C pin placement is determined by the ECCPMX Configuration bit. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY PIC18F8527 52 PIC18F8622 ...
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... Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 427 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 427 Index .................................................................................................................................................................................................. 429 The Microchip Web Site ..................................................................................................................................................................... 441 Customer Change Notification Service .............................................................................................................................................. 441 Customer Support .............................................................................................................................................................................. 441 Reader Response .............................................................................................................................................................................. 442 PIC18F8722 Family Product Identification System............................................................................................................................ 443 DS39646C-page 4 © 2008 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY DS39646C-page 5 ...
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... PIC18F8722 FAMILY NOTES: DS39646C-page 6 © 2008 Microchip Technology Inc. ...
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... Low Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer are minimized. See Section 28.0 “Electrical Characteristics” for values. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY 1.1.2 EXPANDED MEMORY The PIC18F8722 family provides ample room for application code and includes members with 48, 64 128 Kbytes of code space ...
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... Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. See Section 28.0 “Electrical Characteristics” for time-out periods. © 2008 Microchip Technology Inc. ...
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... Extended Instruction Set enabled Packages 64-pin TQFP © 2008 Microchip Technology Inc. PIC18F8722 FAMILY All other features for devices in this family are identical. These are summarized in Table 1-2 and Table 1-2. The pinouts for all devices are listed in Table 1-3 and Table 1-4 ...
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... POR, BOR, POR, BOR, Instruction, RESET Instruction, Stack Full, Stack Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT Yes Yes Yes Yes 75 Instructions; 75 Instructions; 83 with Extended 83 with Extended Instruction Set enabled 80-pin TQFP 80-pin TQFP © 2008 Microchip Technology Inc. ...
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... RG5 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Data Bus<8> Data Latch ...
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... Clock Monitor Timer1 Timer2 Timer3 Timer4 CCP4 CCP5 EUSART1 EUSART2 PORTA (1) RA0:RA7 PORTB (1) RB0:RB7 4 PORTC Access Bank (1) RC0:RC7 12 PORTD (1) RD0:RD7 PORTE (1) RE0:RE7 8 PORTF PRODL (1) RF0:RF7 8 PORTG 8 8 (1) RG0:RG5 8 PORTH 8 (1) RH0:RH7 PORTJ (1) RJ0:RJ7 Comparators MSSP1 MSSP2 © 2008 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input P = Power Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Pin Buffer Type Type Master Clear (input) or programming voltage (input Digital input ...
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... I ST Timer0 external clock input. I/O TTL Digital I/O. I Analog Analog input 4. I Analog High/Low-Voltage Detect input. See the OSC2/CLKO/RA6 pin. See the OSC1/CLKI/RA7 pin. CMOS = CMOS compatible input or output O = Output C™ C/SMBus input buffer Description © 2008 Microchip Technology Inc. ...
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... Input P = Power Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Pin Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. ...
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... EUSART1 asynchronous transmit. I/O ST EUSART1 synchronous clock (see related RX1/DT1). I/O ST Digital I/ EUSART1 asynchronous receive. I/O ST EUSART1 synchronous data (see related TX1/CK1). CMOS = CMOS compatible input or output O = Output C™ C/SMBus input buffer Description 2 C™ mode. © 2008 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input P = Power Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Pin Buffer Type Type PORTD is a bidirectional I/O port. I/O ST Digital I/O ...
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... ECCP1 PWM output C. I/O ST Digital I/O. O — ECCP1 PWM output B. I/O ST Digital I/O. I/O ST Enhanced Capture 2 input/Compare 2 output/ PWM 2 output. O — ECCP2 PWM output A. CMOS = CMOS compatible input or output O = Output C™ C/SMBus input buffer Description © 2008 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input P = Power Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Pin Buffer Type Type PORTF is a bidirectional I/O port. I/O ST Digital I/O ...
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... Ground reference for logic and I/O pins. P — Positive supply for logic and I/O pins. P — Ground reference for analog modules. P — Positive supply for analog modules. CMOS = CMOS compatible input or output O = Output C™ C/SMBus input buffer Description pin. © 2008 Microchip Technology Inc. ...
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... Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Pin Buffer Type Type Master Clear (input) or programming voltage (input). ...
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... Timer0 external clock input. I/O TTL Digital I/O. I Analog Analog input 4. I Analog High/Low-Voltage Detect input. See the OSC2/CLKO/RA6 pin. See the OSC1/CLKI/RA7 pin. CMOS = CMOS compatible input or output O = Output C™/SMB = I C/SMBus input buffer Description © 2008 Microchip Technology Inc. ...
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... Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Pin Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs ...
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... EUSART1 asynchronous transmit. I/O ST EUSART1 synchronous clock (see related RX1/DT1). I/O ST Digital I/ EUSART1 asynchronous receive. I/O ST EUSART1 synchronous data (see related TX1/CK1). CMOS = CMOS compatible input or output O = Output C™/SMB = I C/SMBus input buffer Description 2 C™ mode. © 2008 Microchip Technology Inc. ...
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... Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Pin Buffer Type Type PORTD is a bidirectional I/O port. ...
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... External memory address/data 14. O — ECCP1 PWM output B. I/O ST Digital I/O. I/O TTL External memory address/data 15. I/O ST Enhanced Capture 2 input/Compare 2 output/ PWM 2 output. O — ECCP2 PWM output A. CMOS = CMOS compatible input or output O = Output C™/SMB = I C/SMBus input buffer Description © 2008 Microchip Technology Inc. ...
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... Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Pin Buffer Type Type PORTF is a bidirectional I/O port. ...
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... I/O ST Capture 4 input/Compare 4 output/PWM 4 output. O — ECCP3 PWM output D. I/O ST Digital I/O. I/O ST Capture 5 input/Compare 5 output/PWM 5 output. O — ECCP1 PWM output D. See RG5/MCLR/V PP CMOS = CMOS compatible input or output O = Output C™/SMB = I C/SMBus input buffer Description pin. © 2008 Microchip Technology Inc. ...
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... Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Pin Buffer Type Type PORTH is a bidirectional I/O port. ...
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... Ground reference for logic and I/O pins. P — Positive supply for logic and I/O pins. P — Ground reference for analog modules. P — Positive supply for analog modules. CMOS = CMOS compatible input or output O = Output C™/SMB = I C/SMBus input buffer Description © 2008 Microchip Technology Inc. ...
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... OSC2 pins to establish oscillation. Figure 2-1 shows the pin connections. The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a frequency out of the crystal manufacturer’s specifications. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 2-1: (1) C1 Configuration (1) C2 Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2 ...
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... Clock from Ext. System EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 PIC18FXXXX (HS Mode) Open OSC2 EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI PIC18FXXXX /4 OSC2/CLKO OSC EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) OSC1/CLKI PIC18FXXXX I/O (OSC2) RA6 © 2008 Microchip Technology Inc. ...
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... Recommended values: 3 kΩ ≤ R ≤ 100 kΩ EXT 20 pF ≤ C ≤ 300 pF EXT © 2008 Microchip Technology Inc. PIC18F8722 FAMILY 2.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator ...
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... Locked Loop (PLL) in internal oscillator modes (see Figure 2-10). FIGURE 2-10: /4, OSC (OSCTUNE<6>) INTOSC CLKO OSC2 RA6 by writing to TUN<4:0> in the OSCTUNE register INTOSC AND PLL BLOCK DIAGRAM MHz PLLEN Phase F IN Comparator F OUT Loop Filter ÷4 VCO SYSCLK © 2008 Microchip Technology Inc. ...
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... Minimum frequency Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC Modes” for details. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY 2.6.5 INTOSC FREQUENCY DRIFT The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz ...
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... If the measured time is much greater than the calculated time, the internal oscillator block is running too fast. To compensate, decrement the OSCTUNE register. If the measured time is much less than the calculated time, the internal oscillator block is running too slow. To compensate, increment the OSCTUNE register. © 2008 Microchip Technology Inc. ...
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... Source 8 MHz (INTOSC) INTRC Source 31 kHz (INTRC) © 2008 Microchip Technology Inc. PIC18F8722 FAMILY The secondary oscillators are those external sources not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power-managed mode. The PIC18F8722 family of devices offers the Timer1 oscillator as a secondary oscillator ...
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... The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Clock transitions are discussed in greater detail in Section 3.1.2 “Entering Power-Managed Modes”. © 2008 Microchip Technology Inc. ...
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... Default output frequency of INTOSC on Reset. 4: Modifying the SCS<1:0> bits will cause an immediate clock source switch. 5: Modifying the IRCF<3:0> bits will cause an immediate clock frequency switch if the internal oscillator is providing the device clocks. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY (1) R/W-0 R R-0 ...
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... EC INTIO modes are used as the primary clock source. are listed in OSC1 Pin At logic low (clock/4 output) Configured as PORTA, bit 6 Configured as PORTA, bit 6 Configured as PORTA, bit 6 At logic low (clock/4 output) Feedback inverter disabled at quiescent voltage level (parameter 38, CSD OSC2 Pin © 2008 Microchip Technology Inc. ...
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... Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: • ...
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... Figure 3-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. © 2008 Microchip Technology Inc. ...
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... PRI_RUN RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY n-1 ...
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... The IDLEN and SCS bits are not affected by the switch. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled n-1 n (1) Clock Transition OSC (1) (1) OST T PLL 1 2 n-1 n Clock (2) Transition PC OSTS bit Set . OSC © 2008 Microchip Technology Inc. ...
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... (approx). These intervals are not shown to scale. OST OSC PLL © 2008 Microchip Technology Inc. PIC18F8722 FAMILY 3.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘ ...
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... SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result CSD © 2008 Microchip Technology Inc. ...
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... INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON< ...
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... LP, XT OST HSPLL T OST EC CSD (2) INTOSC T IOBST rc . PLL (parameter 39, Table 28-12), the INTOSC stabilization period. IOBST Clock Ready Status Bit (OSCCON) OSTS (1) IOFS (3) ( OSTS rc (1) (4) IOFS (4) ( OSTS rc (1) IOFS (3) ( OSTS rc (1) (4) IOFS is the PLL Lock-out Timer © 2008 Microchip Technology Inc. ...
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... Ripple Counter Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 4-2 for time-out situations. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 4-1 ...
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... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after POR). DS39646C-page 50 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (2) R/W-0 R/W-0 POR BOR bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... The state of the bit is set to ‘0’ whenever a POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any POR. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 4- ...
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... BOR disabled; must be enabled by reprogramming the Configuration bits. BOR enabled in software; operation controlled by SBOREN. BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. BOR enabled in hardware; must be disabled by reprogramming the Configuration bits. and operates as previously © 2008 Microchip Technology Inc. ...
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... T INTIO1, INTIO2 T Note 1: See parameter 33, Table 28-12 the nominal time required for the PLL to lock. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY 4.5.3 PLL LOCK TIME-OUT With the PLL enabled in its PLL mode, the time-out sequence following a Power-on Reset is slightly differ- ent from other oscillator modes ...
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... INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39646C-page PWRT T OST T PWRT T OST T PWRT T OST © 2008 Microchip Technology Inc RISE < PWRT ): CASE CASE 2 DD ...
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... TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ the nominal time required for the PLL to lock. T PLL © 2008 Microchip Technology Inc. PIC18F8722 FAMILY , V RISE > PWRT T PWRT T OST T PWRT T OST T ...
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... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register SBOREN 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h ( (1) ( STKPTR Register POR BOR STKFUL STKUNF © 2008 Microchip Technology Inc. ...
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... See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY MCLR Resets, Power-on Reset, ...
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... PIC18F8722 FAMILY NOTES: DS39646C-page 62 © 2008 Microchip Technology Inc. ...
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... PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. The program memory map for the PIC18F8722 family of devices is shown in Figure 5-1. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY 5.1.1 PIC18F8527/8622/8627/8722 PROGRAM MEMORY MODES ...
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... From From No Access Yes Yes Yes Yes Yes Yes No Access Yes Yes Yes 21 0000h 0008h 0018h On-Chip PIC18FX722 01FFFFh 1FFFFFh External Program Memory Table Read Table Write To From Yes Yes Yes Yes No Access No Access Yes Yes © 2008 Microchip Technology Inc. ...
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... PIC18F6622 and PIC18F8622. 3: PIC18F6627 and PIC18F8627. 4: PIC18F6722 and PIC18F8722. 5: This is the only mode available on PIC18F6527/6622/6627/6722 devices. 6: Boot block size is determined by the BBSIZ<1:0> bits in CONFIG4L. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Microprocessor Microcontroller with Boot Block Mode Mode 000000h On-Chip Program ...
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... The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. Return Address Stack <20:0> 11111 11110 11101 TOSL 34h 00011 001A34h 00010 Top-of-Stack 000D58h 00001 00000 Stack Pointer STKPTR<4:0> 00010 © 2008 Microchip Technology Inc. ...
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... SP<4:0>: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software POR. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY When the stack has been popped enough times to unload the stack, the next POP will return a value of zero to the PC and set the STKUNF bit, while the Stack Pointer remains at zero ...
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... Multiply get correct offset in table ; Add the modified offset to force jump into table FAST REGISTER STACK CODE EXAMPLE ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK Computed GOTO PCL PCL” instruction does not © 2008 Microchip Technology Inc. ...
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... All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY memory and latched into the instruction register during Q4 ...
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... LSB = 1 LSB = 0 → 0Fh 55h 055h EFh 03h 0006h F0h 00h C1h 23h 123h, 456h F4h 56h 0006h is encoded in the program Word Address ↓ 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h © 2008 Microchip Technology Inc. ...
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... MOVFF 1111 0100 0101 0110 0010 0100 0000 0000 ADDWF © 2008 Microchip Technology Inc. PIC18F8722 FAMILY the instruction sequence. If the first word is skipped for some reason and the second word is executed by itself, a NOP is executed instead. This is necessary for cases when the two-word instruction is preceded by a condi- tional instruction that changes the PC ...
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... This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. © 2008 Microchip Technology Inc. ...
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... Bank 12 FFh = 1101 00h Bank 13 FFh 00h = 1110 Bank 14 FFh 00h = 1111 Bank 15 FFh © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Data Memory Map 000h Access RAM 05Fh 060h GPR 0FFh 100h GPR 1FFh 200h GPR 2FFh 300h GPR ...
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... This is data RAM, which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. (2) From Opcode © 2008 Microchip Technology Inc. ...
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... Unimplemented registers are read as ‘0’. 3: This register is not available on 64-pin devices. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, Resets and interrupts) and those related to the peripheral functions ...
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... N/A 58, 82 N/A 58, 82 N/A 58, 82 N/A 58, 82 N/A 58, 82 58, 82 ---- 0000 58, 82 xxxx xxxx ’ . Reset values are shown for 80-pin devices; 0 ‘ ’ . See Section 2.6.4 “PLL in 0 © 2008 Microchip Technology Inc. ‘ ’ ...
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... RG5 and LATG5 are only available when Master Clear is disabled (MCLRE Configuration bit = 0); otherwise, RG5 and LATG5 read as 6: Bit 7 and Bit 6 are cleared by user software POR. 7: Bit 21 of TBLPTRU allows access to the device Configuration bits. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Bit 4 Bit 3 Bit 2 — ...
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... LATD0 60, 143 xxxx xxxx LATC1 LATC0 60, 140 xxxx xxxx LATB1 LATB0 60, 137 xxxx xxxx LATA1 LATA0 60, 135 xxxx xxxx ’ . Reset values are shown for 80-pin devices; 0 ‘ ’ . See Section 2.6.4 “PLL in 0 © 2008 Microchip Technology Inc. ‘ ’ ...
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... RG5 and LATG5 are only available when Master Clear is disabled (MCLRE Configuration bit = 0); otherwise, RG5 and LATG5 read as 6: Bit 7 and Bit 6 are cleared by user software POR. 7: Bit 21 of TBLPTRU allows access to the device Configuration bits. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Bit 4 Bit 3 Bit 2 ...
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... Table 26-2 and Table 26-3. Note: The C and DC bits operate as the borrow and digit borrow bits, respectively, in subtraction. R/W-x R/W-x R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-x R/W-x (1) ( bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Purpose Register File” location in the Access Bank (Section 5.3.2 “Access Bank”) as the data source for the instruction. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR (Section 5.3.1 “ ...
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... FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g OV, etc.). ADDWF, INDF1, 1 FSR1H:FSR1L 000h Bank 0 100h Bank 1 200h Bank 2 300h 0 Bank 3 through Bank 13 E00h Bank 14 F00h Bank 15 FFFh Data Memory © 2008 Microchip Technology Inc. ...
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... Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect Addressing with FSR0 and FSR1 also remain unchanged. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY 5.5.1 INDEXED ADDRESSING WITH LITERAL OFFSET ...
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... F00h Bank 15 F80h SFRs FFFh Data Memory BSR 000h 00000000 Bank 0 080h 100h 001001da Bank 1 through Bank 14 F00h Bank 15 F80h SFRs FFFh Data Memory © 2008 Microchip Technology Inc. 00h 60h 80h Valid range for ‘f’ FFh ffffffff FSR2L ffffffff ...
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... F80h by using the BSR. FFFh © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before ...
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... PIC18F8722 FAMILY NOTES: DS39646C-page 86 © 2008 Microchip Technology Inc. ...
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... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1:Table Pointer register points to a byte in program memory. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
Page 90
... The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Note: The EEIF interrupt flag bit (PIR2<4>) is set When set, when the write is complete. It must be cleared in software. Table Latch (8-bit) TABLAT © 2008 Microchip Technology Inc. ...
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... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY R/W-0 R/W-x R/W-0 ...
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... TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TBLPTR<21:6> TABLE READ – TBLPTR<21:0> TBLPTRL 0 TABLE WRITE TBLPTR<5:0> © 2008 Microchip Technology Inc. ...
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... WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVF WORD_ODD © 2008 Microchip Technology Inc. PIC18F8722 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
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... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts © 2008 Microchip Technology Inc. ...
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... EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN to enable byte writes. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY The long write is necessary for programming the inter- nal Flash. Instruction execution is halted while in a long write cycle ...
Page 96
... TBLWT holding register. ; loop until buffers are full © 2008 Microchip Technology Inc. ...
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... CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: Bit 21 of TBLPTRU allows access to the device Configuration bits. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY ; point to Flash program memory ; access Flash program memory ; enable write to memory ...
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... PIC18F8722 FAMILY NOTES: DS39646C-page 96 © 2008 Microchip Technology Inc. ...
Page 99
... Note: For the sake of clarity, only I/O port and external bus assignments are shown here. One or more additional multiplexed features may be available on some pins. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY The bus is implemented with 28 pins, multiplexed across four I/O ports. Three ports (PORTD, PORTE ...
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... Byte Select mode: TABLAT data copied on both MSB and LSB; WRH and (UB or LB) will activate R/W-0 U-0 U-0 WAIT0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 WM1 WM0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F8722 FAMILY 7.2.1 21-BIT ADDRESSING As an extension of 20-bit address width operation, the External Memory Bus can also fully address a 2 Mbyte memory space. This is done by using the Bus Address bit 0 (BA0) control line as the Least Significant bit of the address ...
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... BA0 for the byte address line and one I/O line to select between Byte and Word mode. The other 16-bit modes do not need BA0. JEDEC standard static RAM memories will use the signals for byte selection. © 2008 Microchip Technology Inc. register ...
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... Upper-order address lines are used only for 20-bit address widths. 2: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY During a TBLWT instruction cycle, the TABLAT data is presented on the upper and lower bytes of the AD< ...
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... A<20:1> 373 D<15:0> 373 cycle to an odd address JEDEC Word A<x:0> EPROM Memory D<15:0> ( Address Bus Data Bus Control Lines © 2008 Microchip Technology Inc. ...
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... Upper-order address lines are used only for 20-bit address width. 3: Demultiplexing is only required when multiple memory devices are accessed. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC standard Flash memories require that a controller I/O port pin be connected to the memory’ ...
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... TBLRD Cycle 0Ch CF33h Opcode Fetch TBLRD 92h MOVLW 55h from 199E67h from 000102h TBLRD Cycle 1 TBLRD Cycle 2 WAIT STATE 9256h ‘1’ ‘1’ ‘0’ Wait 9256h Opcode Fetch ADDLW 55h from 000104h MOVLW © 2008 Microchip Technology Inc. ...
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... CE ALE OE Memory Opcode Fetch Cycle SLEEP from 007554h Instruction INST(PC – 2) Execution Note 1: Bus becomes inactive regardless of power-managed mode entered when © 2008 Microchip Technology Inc. PIC18F8722 FAMILY 00h 0E55h 3AABh Opcode Fetch Sleep Mode, MOVLW 55h from 007556h ...
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... This generally includes basic EPROM and Flash devices. It allows table writes to byte-wide external memories. The appropriate level of BA0 control line is strobed on the LSb of the TBLPTR. D<7:0> A<19:0> A<x:1> 373 A0 D<15:8> D<7:0> Address Bus Data Bus Control Lines © 2008 Microchip Technology Inc. (2) WR ...
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... AD<7:0> CE ALE OE Opcode Fetch Memory Cycle TBLRD * from 000100h Instruction INST(PC – 2) Execution Note 1: The address lines actually used depends on the address width selected. This example assumes 20-bit addressing. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY 03Ah CCFh ABh 55h 0Eh ...
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... Note 1: The address lines actually used depends on the address width selected. This example assumes 16-bit addressing. DS39646C-page 108 00h 3Ah ABh 55h 0Eh Sleep Mode, Opcode Fetch MOVLW 55h from 007556h SLEEP SLEEP 03Ah 55h 0Eh Opcode Fetch MOVLW 55h from 007556h (2) Bus Inactive is executed. Q4 55h ‘ 1 ’ © 2008 Microchip Technology Inc. ...
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... Note 1: This register is not implemented on 64-pin devices. 2: Unimplemented in PIC18F6527/6622/6627/6722 devices. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY In Sleep and Idle modes, the microcontroller core does not need to access data; bus operations are sus- pended. The state of the external bus is frozen with the ...
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... PIC18F8722 FAMILY NOTES: DS39646C-page 110 © 2008 Microchip Technology Inc. ...
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... EEPROM for read and write operations. EEADRH holds the two MSbs of the address; the upper 6 bits are ignored. The 10-bit range of the pair can address a memory range of 1024 bytes (00h to 3FFh). © 2008 Microchip Technology Inc. PIC18F8722 FAMILY 8.2 EECON1 and EECON2 Registers Access to the data EEPROM is controlled by two registers: EECON1 and EECON2 ...
Page 114
... When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS39646C-page 112 R/W-0 R/W-x R/W-0 (1) FREE WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/S-0 R/S bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... EECON1, WR BSF INTCON, GIE BCF EECON1, WREN © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code exe- cution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM ...
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... Loop to refresh array ; Read current address ; ; Write 55h ; ; Write 0AAh ; Set WR bit to begin write ; Wait for write to complete ; Increment address ; Not zero again ; Increment the high address ; Not zero again ; Disable writes ; Enable interrupts information (e.g., program © 2008 Microchip Technology Inc. ...
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... CFGS IPR2 OSCFIP CMIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — — — ...
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... PIC18F8722 FAMILY NOTES: DS39646C-page 116 © 2008 Microchip Technology Inc. ...
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... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2008 Microchip Technology Inc. PIC18F8722 FAMILY EXAMPLE 9- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL ...
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... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H © 2008 Microchip Technology Inc. ...
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... Individual interrupts can be disabled through their corresponding enable bits. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ® ...
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... IPEN GIEL/PEIE IPEN TMR0IF IPEN TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP © 2008 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIEH/GIE Interrupt to CPU Vector to Location 0018h GIEH/GIE GIEL/PEIE ...
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... None of the RB7:RB4 pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Note: Interrupt flag bits are set when an interrupt ...
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... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39646C-page 122 R/W-1 R/W-1 R/W-1 INTEDG2 INTEDG3 TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY R/W-0 ...
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... R-0 R/W-0 R/W-0 TX1IF SSP1IF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... A TMR1/TMR3 register capture occurred (must be cleared in software TMR1/TMR3 register capture occurred Compare mode TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY R/W-0 R/W-0 R/W-0 EEIF BCL1IF HLVDIF U = Unimplemented bit, read as ‘ ...
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... No TMR register compare match occurred PWM mode: Not used in PWM mode. DS39646C-page 126 R-0 R/W-0 R/W-0 TX2IF TMR4IF CCP5IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 CCP4IF CCP3IF bit Bit is unknown 2 C™ master was © 2008 Microchip Technology Inc. ...
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... Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt © 2008 Microchip Technology Inc. PIC18F8722 FAMILY R/W-0 R/W-0 R/W-0 TX1IE SSP1IE CCP1IE U = Unimplemented bit, read as ‘ ...
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... TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: ECCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled DS39646C-page 128 R/W-0 R/W-0 R/W-0 EEIE BCL1IE HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 TMR3IE CCP2IE bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Enabled 0 = Disabled bit 1 CCP4IE: CCP4 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP3IE: ECCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled © 2008 Microchip Technology Inc. PIC18F8722 FAMILY R-0 R/W-0 R/W-0 TX2IE TMR4IE CCP5IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 ...
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... Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority DS39646C-page 130 R/W-1 R/W-1 R/W-1 TX1IP SSP1IP CCP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2008 Microchip Technology Inc. PIC18F8722 FAMILY R/W-1 R/W-1 R/W-1 EEIP BCL1IP HLVDIP U = Unimplemented bit, read as ‘0’ ...
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... Low priority bit 0 CCP3IP: ECCP3 Interrupt Priority bit 1 = High priority 0 = Low priority DS39646C-page 132 R/W-1 R/W-1 R/W-1 TX2IP TMR4IP CCP5IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 CCP4IP CCP3IP bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... For details of bit operation, see Register 4-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-1. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY R/W-1 R-1 R Unimplemented bit, read as ‘ ...
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... Example 10-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS © 2008 Microchip Technology Inc. ...
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... Port Note 1: I/O pins have diode protection © 2008 Microchip Technology Inc. PIC18F8722 FAMILY 11.1 PORTA, TRISA and LATA Registers PORTA is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i ...
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... Bit 2 RA5 RA4 RA3 RA2 LATA5 LATA4 LATA3 LATA2 TRISA5 TRISA4 TRISA3 TRISA2 VCFG1 VCFG0 PCFG3 PCFG2 Description /4) in all oscillator modes except RC, Reset Bit 1 Bit 0 Values on page RA1 RA0 61 LATA1 LATA0 60 TRISA1 TRISA0 60 PCFG1 PCFG0 59 © 2008 Microchip Technology Inc. ...
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... RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Four of the PORTB pins (RB<7:4>) have an interrupt-on-change feature. Only pins configured as inputs can cause this interrupt to occur (i ...
Page 140
... LATB<7> data output. I TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared. I TTL Interrupt-on-pin change. O DIG Serial execution data output for ICSP and ICD operation I ST Serial execution data input for ICSP and ICD operation Description (2) . (2) . (2) . © 2008 Microchip Technology Inc. ...
Page 141
... TRISB TRISB7 TRISB6 INTCON GIE/GIEH PEIE/GIEL TMR0IE INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INTCON3 INT2IP INT1IP Legend: Shaded cells are not used by PORTB. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 LATB5 LATB4 ...
Page 142
... EXAMPLE 11-3: CLRF PORTC CLRF LATC MOVLW 0CFh peripheral MOVWF TRISC INITIALIZING PORTC ; Initialize PORTC by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs © 2008 Microchip Technology Inc. ...
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... I C/SMB = I C/SMBus input buffer Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignment for ECCP2 when CCP2MX Configuration bit is set. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY I/O I/O Type O DIG LATC< ...
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... Synchronous serial data input (EUSART1 module). User must configure as an input. Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 LATC5 LATC4 LATC3 LATC2 TRISC5 TRISC4 TRISC3 TRISC2 Description Reset Bit 1 Bit 0 Values on page RC1 RC0 60 LATC1 LATC0 60 TRISC1 TRISC0 60 © 2008 Microchip Technology Inc. ...
Page 145
... When the interface is enabled, PORTD is the low-order byte of the multiplexed address/data bus (AD<7:0>). The TRISD bits are also overridden. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY PORTD can also be configured to function as an 8-bit wide parallel microprocessor port by setting the PSPMODE control bit (PSPCON<4>). In this mode, parallel port data takes priority over other digital I/O (but not the external memory interface) ...
Page 146
... External memory interface, data bit 4 input. O DIG PSP read data output (LATD<4>). Takes priority over port and PSP data. I TTL PSP write data input. O DIG SPI data output (MSSP2 module). Takes priority over PSP and port data. Description © 2008 Microchip Technology Inc. ...
Page 147
... SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Name Bit 7 Bit 6 PORTD RD7 RD6 LATD LATD7 LATD6 TRISD TRISD7 TRISD6 © 2008 Microchip Technology Inc. PIC18F8722 FAMILY I/O I/O Type O DIG LATD<5> data output PORTD<5> data input. O DIG External memory interface, address/data bit 5 output. Takes priority over PSP, MSSP and port data ...
Page 148
... EXAMPLE 11-5: INITIALIZING PORTE CLRF PORTE ; Initialize PORTE by ; clearing output ; data latches CLRF LATE ; Alternate method ; to clear output ; data latches MOVLW 03h ; Value used to ; initialize data ; direction MOVWF TRISE ; Set RE<1:0> as inputs ; RE<7:2> as outputs © 2008 Microchip Technology Inc. ...
Page 149
... TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate assignment for ECCP2 when CCP2MX Configuration bit is cleared (all devices in Microcontroller mode). 2: Implemented on 80-pin devices only. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY I/O I/O Type ...
Page 150
... May be configured for tri-state during Enhanced PWM shutdown events. Bit 5 Bit 4 Bit 3 Bit 2 RE5 RE4 RE3 RE2 LATE5 LATE4 LATE3 LATE2 TRISE4 TRISE3 TRISE2 Description Reset Bit 1 Bit 0 Values on page RE1 RE0 60 LATE1 LATE0 60 TRISE1 TRISE0 60 © 2008 Microchip Technology Inc. ...
Page 151
... RF2 may be used as comparator inputs or outputs by setting the appropriate bits in the CMCON register. To use RF<6:0:> as digital inputs necessary to turn off the A/D inputs. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Note Power-on Reset, the RF<6:0> pins are configured as analog inputs and read as ‘ ...
Page 152
... TRISF5 TRISF4 TRISF3 TRISF2 RF5 RF4 RF3 RF2 LATF5 LATF4 LATF3 LATF2 VCFG1 VCFG0 PCFG3 PCFG2 C2INV C1INV CIS CM2 Description Reset Bit 1 Bit 0 Values on page TRISF1 TRISF0 60 RF1 RF0 60 LATF1 LATF0 60 PCFG1 PCFG0 59 CM1 CM0 59 © 2008 Microchip Technology Inc. ...
Page 153
... The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY The sixth pin of PORTG (RG5/MCLR/V only pin. Its operation is controlled by the MCLRE Configuration bit. When selected as a port pin (MCLRE = 0), it functions as a digital input only pin ...
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... I ST PORTG<5> data input; enabled when MCLRE Configuration bit is clear External Master Clear input; enabled when MCLRE Configuration bit is set. I ANA High-voltage detection; used for ICSP™ mode entry detection. Always available regardless of pin mode. Description © 2008 Microchip Technology Inc. ...
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... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG. Note 1: RG5 and LATG5 are only available when MCLR is disabled (MCLRE Configuration bit = 0; otherwise, RG5 and LATG5 read as ‘0’. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Bit 5 Bit 4 ...
Page 156
... EXAMPLE 11-8: CLRF PORTH CLRF LATH MOVLW 0CFh MOVWF TRISH INITIALIZING PORTH ; Initialize PORTH by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RH3:RH0 as inputs ; RH5:RH4 as outputs ; RH7:RH6 as inputs © 2008 Microchip Technology Inc. ...
Page 157
... TRISH TRISH7 TRISH6 PORTH RH7 RH6 LATH LATH7 LATH6 ADCON1 — — © 2008 Microchip Technology Inc. PIC18F8722 FAMILY I/O Type DIG LATH<0> data output PORTH<0> data input. DIG External memory interface, address line 16. Takes priority over port data. DIG LATH<1> data output. ...
Page 158
... EXAMPLE 11-9: CLRF PORTJ CLRF LATJ MOVLW 0xCF MOVWF TRISJ INITIALIZING PORTJ ; Initialize PORTJ by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RJ3:RJ0 as inputs ; RJ5:RJ4 as output ; RJ7:RJ6 as inputs © 2008 Microchip Technology Inc. ...
Page 159
... TABLE 11-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ Name Bit 7 Bit 6 PORTJ RJ7 RJ6 LATJ LATJ7 LATJ6 TRISJ TRISJ7 TRISJ6 © 2008 Microchip Technology Inc. PIC18F8722 FAMILY I/O I/O Type O DIG LATJ<0> data output PORTJ<0> data input. O DIG External memory interface address latch enable control output. Takes priority over digital I/O ...
Page 160
... WR LATD CKx or PORTD Data Latch PORTD EN EN TRIS Latch RD LATD One bit of PORTD Set Interrupt Flag PSPIF (PIR1<7>) Read Chip Select Write Note: I/O pin has protection diodes to V © 2008 Microchip Technology Inc. RDx pin TTL RD TTL CS TTL WR TTL and ...
Page 161
... A write occurred when a previously input word has not been read (must be cleared in software overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode bit 3-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC18F8722 FAMILY R/W-0 U-0 U-0 PSPMODE — — ...
Page 162
... RC1IE TX1IE SSP1IE CCP1IE RC1IP TX1IP SSP1IP CCP1IP Reset Bit 1 Bit 0 Values on page RD1 RD0 60 LATD1 LATD0 60 TRISD1 TRISD0 60 RE1 RE0 60 LATE1 LATE0 60 TRISE1 TRISE0 60 — — — 59 INT0IF RBIF 57 TMR2IF TMR1IF 60 TMR2IE TMR1IE 60 TMR2IP TMR1IP 60 © 2008 Microchip Technology Inc. ...
Page 163
... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2008 Microchip Technology Inc. PIC18F8722 FAMILY The T0CON register (Register 12-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 12-1 ...
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... Sync with Internal TMR0L Clocks Delay There is a delay between OSC Set TMR0IF TMR0L on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus © 2008 Microchip Technology Inc. ...
Page 165
... Legend: Shaded cells are not used by Timer0. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY 12.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “ ...
Page 166
... PIC18F8722 FAMILY NOTES: DS39646C-page 164 © 2008 Microchip Technology Inc. ...
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... OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2008 Microchip Technology Inc. PIC18F8722 FAMILY A simplified block diagram of the Timer1 module is shown in Figure 13-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 13-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
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... Special Event Trigger Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR1H 8 8 Internal Data Bus © 2008 Microchip Technology Inc. ...
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... C1 PIC18FXXXX 27 pF T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 13-1 for additional information about capacitor selection. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 13-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Osc Type Freq C1 ( kHz 27 pF Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
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... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. © 2008 Microchip Technology Inc. ...
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... Timer1 Register High Byte T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: Shaded cells are not used by the Timer1 module. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ...
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... PIC18F8722 FAMILY NOTES: DS39646C-page 170 © 2008 Microchip Technology Inc. ...
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... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2008 Microchip Technology Inc. PIC18F8722 FAMILY 14.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by- 16 prescale options ...
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... Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TX1IF SSP1IF CCP1IF TX1IE SSP1IE CCP1IE TX1IP SSP1IP CCP1IP Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 57 TMR2IF TMR1IF 60 TMR2IE TMR1IE 60 TMR2IP TMR1IP © 2008 Microchip Technology Inc. ...
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... OSC bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2008 Microchip Technology Inc. PIC18F8722 FAMILY A simplified block diagram of the Timer3 module is shown in Figure 15-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 15-2. The Timer3 module is controlled through the T3CON register (Register 15-1) ...
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... Clear TMR3 TMR3L 8 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR3H 8 8 Internal Data Bus © 2008 Microchip Technology Inc. ...
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... T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY 15.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
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... PIC18F8722 FAMILY NOTES: DS39646C-page 176 © 2008 Microchip Technology Inc. ...
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... Timer4 is off bit 1-0 T4CKPS<1:0>: Timer4 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2008 Microchip Technology Inc. PIC18F8722 FAMILY 16.1 Timer4 Operation Timer4 can be used as the PWM time base for the PWM mode of the CCP modules. The TMR4 register is readable and writable and is cleared on any device Reset ...
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... Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TX2IP TMR4IP CCP5IP TX2IF TMR4IF CCP5IF TX2IE TMR4IE CCP5IE Sets Flag bit TMR4IF (1) Reset Bit 1 Bit 0 Values on page INT0IF RBIF 57 CCP4IP CCP3IP 60 CCP4IF CCP3IF 60 CCP4IE CCP3IE 60 61 T4CKPS1 T4CKPS0 61 61 © 2008 Microchip Technology Inc. ...
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... Compare mode, trigger special event; CCPxIF bit is set, CCPx pin is unaffected (For the effects of the trigger, see Section 17.3.4 “Special Event Trigger”.) 11xx = PWM mode © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Capture and Compare operations described in this chap- ter apply to all standard and Enhanced CCP modules ...
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... Timer3 is used for all Capture and Compare operations for all CCP modules. Timer4 is used for PWM operations for all CCP modules. Modules may share either timer resource as a common time base. Timer1 and Timer2 are not available. © 2008 Microchip Technology Inc. ...
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... RG3/CCP4 pin and Edge Detect CCP1CON<3:0> Q’s © 2008 Microchip Technology Inc. PIC18F8722 FAMILY 17.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false inter- rupts ...
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... The ECCP2 Special Event Trigger can also start an A/D conversion. In order to do this, the A/D converter must already be enabled. Set Flag bit CCP4IF Output Logic Match T3CCP2 Mode Select TMR1H Special Event Trigger mode CCPR4H CCPR4L Comparator 1 0 TMR1L TMR3H TMR3L © 2008 Microchip Technology Inc. ...
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... P3M0 CCP4CON — — CCP5CON — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3. Note 1: Implemented on 80-pin devices only. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — ...
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... CCPRxH until after a match between PR2 (PR4) and TMR2 (TMR4) occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register. • OSC (TMR2 Prescale Value) “Timer2 Module” and T • (TMR2 Prescale Value) OSC © 2008 Microchip Technology Inc. ...
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... EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz Timer Prescaler (1, 4, 16) PR2 Value FFh Maximum Resolution (bits) © 2008 Microchip Technology Inc. PIC18F8722 FAMILY 17.4.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. ...
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... CCP5IP DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 Reset Bit 2 Bit 1 Bit 0 Values on page INT0IF RBIF 57 PD POR BOR 56 TMR2IF TMR1IF 60 TMR2IE TMR1IE 60 TMR2IP TMR1IP 60 CCP4IF CCP3IF 60 CCP4IE CCP3IE 60 CCP4IP CCP3IP © 2008 Microchip Technology Inc. ...
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... PWM mode: PxA, PxC active-high; PxB, PxD active-low 1110 = PWM mode: PxA, PxC active-low; PxB, PxD active-high 1111 = PWM mode: PxA, PxC active-low; PxB, PxD active-low © 2008 Microchip Technology Inc. PIC18F8722 FAMILY The control register for the Enhanced CCP modules is shown in Register 18-1 ...
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... Enhanced CCP module regardless of the program memory mode. The final option is that the ABW<1:0> Configuration bits can be used to select 8, 12 20-bit EMB addressing. Pins not assigned to EMB address pins are available for peripheral or port functions. © 2008 Microchip Technology Inc. devices, the ...
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... Don’t care, N/A = Not available. Shaded cells indicate pin assignments not used by ECCP1 in a given mode. Note 1: With ECCP1 in Quad PWM mode, the CCP5 module’s output overrides P1D. 2: The EMB address bus width will determine whether the pin will perform an EMB or port/peripheral function. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY RC2 RE6 RE5 ...
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... RE0 P2B RE1 RE0 P2B P2C P2D RE2 RE1 RE0 P2B RE1 RE0 P2B P2C P2D (1) (1) (1) AD10 AD9 AD8 (1) (1) (1) AD9 AD8 (1) (1) (1) AD9/P2C P2D/AD8 (1) (1) (1) AD10 AD9 AD8 (1) (1) (1) AD9 AD8 (1) (1) (1) AD9/P2C P2D/AD8 © 2008 Microchip Technology Inc. ...
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... Don’t care, N/A = Not available. Shaded cells indicate pin assignments not used by ECCP3 in a given mode. Note 1: With ECCP3 in Quad PWM mode, the CCP4 module’s output overrides P3D. 2: The EMB address bus width will determine whether the pin will perform an EMB or port/peripheral function. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY RG0 RE4 RE3 ...
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... The Timer2 postscaler (see Section 14.0 “Timer2 Module”) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. and register ). OSC • OSC (TMR2 Prescale Value) © 2008 Microchip Technology Inc. ...
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... In PWM mode, CCPR1H is a read-only register. TABLE 18-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz Timer Prescaler (1, 4, 16) PR2 Value FFh Maximum Resolution (bits) © 2008 Microchip Technology Inc. PIC18F8722 FAMILY P1M1<1:0> CCP1M<3:0> ECCP1/P1A P1B Output R ...
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... Section 18.4 “Enhanced PWM Mode”. The Half-Bridge and Full-Bridge Output modes are covered in detail in the sections that follow. The general relationship of the outputs in all configurations is summarized in Figure 18-2. 0 Duty Cycle Period (1) (1) Delay Delay © 2008 Microchip Technology Inc. PR2 + 1 ...
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... OSC • Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 18.4.6 “Programmable Dead-Band Delay”). © 2008 Microchip Technology Inc. PIC18F8722 FAMILY 0 Duty Cycle Period (1) (1) Delay Delay ...
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... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. V+ FET Driver P1A Load FET Driver P1B V- V+ FET Driver Load FET Driver V- HALF-BRIDGE PWM OUTPUT Period td (1) ( FET Driver FET Driver © 2008 Microchip Technology Inc. ...
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... Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2008 Microchip Technology Inc. PIC18F8722 FAMILY P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2>, PORTE<6:5> and PORTG<4> data latches. Alternatively, P1B and P1C can be assigned to PORTH< ...
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... Reduce PWM for a PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. QC FET Driver FET Driver QD © 2008 Microchip Technology Inc. ...