ADZS-21469-EZBRD Analog Devices Inc, ADZS-21469-EZBRD Datasheet
ADZS-21469-EZBRD
Specifications of ADZS-21469-EZBRD
Related parts for ADZS-21469-EZBRD
ADZS-21469-EZBRD Summary of contents
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Preliminary Technical Data SUMMARY Note: This datasheet is preliminary. This document contains material that is subject to change without notice. High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Single-instruction, multiple-data (SIMD) computational architecture On-chip memory—5 Mbits ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 KEY FEATURES PROCESSOR CORE — 450 MHz core instruction rate, the processor per- forms at 2.7 GFLOPS/900 MMACs 5 Mbits on-chip RAM, 4 Mbits on-chip ROM for simultaneous access by the core processor and DMA DDR2 ...
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Preliminary Technical Data TABLE OF CONTENTS Summary ............................................................... 1 Key Features—Processor Core ................................. 2 Input/Output Features ........................................... 2 Table Of Contents .................................................... 3 General Description ................................................. 4 Family Core Architecture ....................................... 5 Memory ............................................................. 6 External Memory .................................................. 6 Input/Output ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 GENERAL DESCRIPTION The ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 ® SHARC processors are members of the SIMD SHARC family of DSPs that feature Analog Devices' Super Harvard Architec- ture. The processors are source code compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x, and ADSP-2116x DSPs as ...
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Preliminary Technical Data Table 2 shows performance benchmarks for the ADSP-2146x processors. Table 2. Processor Benchmarks Benchmark Algorithm 1024 Point Complex FFT (Radix 4, With Reversal) 20.44 μs 1 FIR Filter (per Tap) 1 IIR Filter (per Biquad) Matrix Multiply ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. Instruction Cache The ADSP-2146x includes an on-chip instruction cache that ...
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Preliminary Technical Data to four separate devices to coexist, supporting any desired com- bination of synchronous and asynchronous device types. Non DDR2 DRAM external memory address space is shown in Table 5. External Memory Execution In the ADSP-2146x, the program ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Table 4. ADSP-21462W/ADSP-21469/ADSP-21469W Internal Memory Space IOP Registers 0x0000 0000–0x0003 FFFF Extended Precision Normal or Long Word (64 bits) Instruction Word (48 bits) BLOCK 0 RAM BLOCK 0 RAM 0x0004 9000–0x0004 EFFF 0x0008 C000-0x0009 3FFF Reserved Reserved 0x0004 F000–0x0005 ...
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Preliminary Technical Data lines. Bank 0 occupies a 14M word window and banks 1, 2, and 3 occupy a 16M word window in the processor’s address space but, if not fully populated, these windows are not made contigu- ous by ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 2 • Packed I S mode • Left-justified mode Left-justified mode is a mode where in each frame sync cycle two samples of data are transmitted/received—one sample on the high segment of the frame sync, the other on the ...
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Preliminary Technical Data • Supporting data formats from bits per frame. • Both transmit and receive operations can be configured to generate maskable interrupts to the processor. In conjunction with the general-purpose timer functions, auto- baud detection ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Note that the analog supply pin (V DD_A internal clock generator PLL. To produce a stable clock rec- ommended that PCB designs use an external filter circuit for the V pin. Place the filter components as close ...
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Preliminary Technical Data PIN FUNCTION DESCRIPTIONS The following symbols appear in the Type column asynchronous input output synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state, (pd) ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Table 7. Pin List (Continued) Name Type DDR2_BA O/T 2-0 DDR2_CAS O/T DDR2_CKE O/T DDR2_CS O/T 3-0 DDR2_DATA I/O/T 15-0 DDR2_DM O/T 1-0 DDR2_DQS I/O/T (Differential) 1-0 DDR2_DQS 1-0 DDR2_RAS O/T DDR2_WE O/T DDR2_CLK0, O/T (Differential) DDR2_CLK0, DDR2_CLK1, DDR2_CLK1 ...
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Preliminary Technical Data Table 7. Pin List (Continued) Name Type LDAT0 I/0 7–0 LDAT1 7–0 LCLK0 I/O LCLK1 LACK0 I/O LACK1 THD_P I THD_M TDI I (pu) TDO TMS I (pu) TCK I ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Table 7. Pin List (Continued) Name Type CLKIN I CLKOUT/ I/O (pu) RESETOUT/ RUNRSTIN 3 MLBCLK I (pd) 3 MLBDAT I/O (pd pin mode. Input in 5 pin mode. 3 MLBSIG I/O (pd pin mode. ...
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Preliminary Technical DATA MODES The address and data pins of the external memory interface are muxed (using bits in the SYSCTL register) to support the external memory interface data (input/output), the PDAP (input only), and the FLAGS (input/output). Table 8. ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 SPECIFICATIONS OPERATING CONDITIONS 1 Parameter Description V Internal (Core) Supply Voltage DD_INT V External (I/O) Supply Voltage DD_EXT 4 V DDR2 Controller Supply Voltage DD_DDR2 V DDR2 Reference Voltage REF 5 V High Level Input Voltage @ V IH ...
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Preliminary Technical Data ELECTRICAL CHARACTERISTICS 1 Parameter Description 2 V High Level Output OH Voltage 2 V Low Level Output OL Voltage 4 I Output Source DC OH_DDR2 Current 4 I Output Sink DC Current OL_DDR2 V OH_DDR2 V OL_DDR2 ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 MAXIMUM POWER DISSIPATION See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-2146x SHARC Processors” for detailed thermal and power information regarding maximum power dissipation. For information on package thermal specifications, see Characteristics on Page 53. ABSOLUTE MAXIMUM RATINGS Stresses greater ...
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Preliminary Technical Data Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Power-Up Sequencing The timing requirements for processor startup are given in Table 14. Table 14. Power Up Sequencing Timing Requirements (Processor Startup) Parameter Timing Requirements t RESET Low Before V RSTVDD Before V EVDD-DDR2VDD DD_EXT t ...
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Preliminary Technical Data Clock Input Table 15. Clock Input Parameter Timing Requirements t CLKIN Period CK t CLKIN Width Low CKL t CLKIN Width High CKH t CLKIN Rise/Fall (0 2.0 V) CKRF 3 t CCLK Period CCLK ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Reset Table 16. Reset Parameter Timing Requirements 1 t RESET Pulse Width Low WRST t RESET Setup Before CLKIN Low SRST 1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more ...
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Preliminary Technical Data Interrupts The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts as well as the DAI_P20-1 and DPI_P14-1 pins when they are configured as interrupts. ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Timer WDTH_CAP Timing The following timing specification applies to timer0 and timer1, and in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DPI_P14–1 pins through the SRU. Therefore, the timing specification provided below is ...
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Preliminary Technical Data Precision Clock Generator (Direct Pin Routing) This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Flags The timing specifications provided below apply to AMI_ADDR23-0 and AMI_DATA7-0 when configured as FLAGS. See Table 7 on page 13 for more information on flag use. Table 24. Flags Parameter Timing Requirement t DPI_P14-1, AMI_ADDR23-0, AMI_DATA7-0, FLAG3–0 IN ...
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Preliminary Technical Data DDR2 SDRAM Read Cycle Timing Table 25. DDR2 SDRAM Read Cycle Timing, V Parameter Symbol Timing Requirements TBD TBD ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 nominal 1.8V DD-DDR2 TBD Figure 16. DDR2 SDRAM Controller Input AC Timing Rev. PrC | Page 29 ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 DDR2 SDRAM Write Cycle Timing Table 26. DDR2 SDRAM Write Cycle Timing, V Parameter Symbol Switching Characteristics TBD TBD nominal 1.8V DD-DDR2 TBD Figure 17. DDR2 SDRAM Controller Output AC Timing Rev. PrC | Page ...
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Preliminary Technical Data Memory Read Bus Master — Use these specifications for asynchronous interfacing to memo- ries. Note that timing for AMI_ACK, AMI_DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asyn- chronous access mode. Table 27. Memory Read ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Memory Write Bus Master — Use these specifications for asynchronous interfacing to memo- ries. Note that timing for AMI_ACK, AMI_DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asyn- chronous access mode. Table 28. Memory Write — Bus ...
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Preliminary Technical Data Link Ports Calculation of link receiver data setup and hold relative to link clock is required to determine the maximum allowable skew that can be introduced in the transmission path between LDATA and LCLK. Setup skew is ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Table 30. Link Ports – Transmit Parameter Timing Requirements t LACK Setup Before LCLK High SLACH t LACK Hold After LCLK High HLACH Switching Characteristics t Data Delay After LCLK High DLDCH t Data Hold After LCLK High HLDCH ...
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Preliminary Technical Data Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Table 33. Serial Ports—Enable and Three-State Parameter Switching Characteristics 1 t Data Enable from External Transmit SCLK DDTEN 1 t Data Disable from External Transmit SCLK DDTTE 1 t Data Enable from Internal Transmit SCLK DDTIN 1 Referenced to ...
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Preliminary Technical Data DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE t SCLKIW - DAI_P20 1 (SCLK) t DFSIR t HOFSIR - DAI_P20 1 (FS) - DAI_P20 1 (DATA CHANNEL A/B) NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL) OR ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Input Data Port (IDP) The timing requirements for the IDP are given in signals (SCLK, FS, and SDATA) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications pro- vided below are valid at the DAI_P20–1 ...
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Preliminary Technical Data Sample Rate Converter—Serial Input Port The ASRC input signals (SCLK, FS, and SDATA) are routed from the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided in Table 36 are valid at the DAI_P20–1 pins. Table ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Sample Rate Converter—Serial Output Port For the serial output port, the frame-sync is an input and it should meet setup and hold times with regard to SCLK on the output port. The serial data output, SDATA, has a hold ...
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Preliminary Technical Data Parallel Data Acquisition Port (PDAP) The timing requirements for the PDAP are provided in Table 38. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the PDAP, see ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Pulse-Width Modulation Generators (PWM) The following timing specifications apply when the AMI_ADDR23-8 pins are configured as PWM. Table 39. Pulse-Width Modulation (PWM) Timing Parameter Switching Characteristics t PWM Output Pulse Width PWMW t PWM Output Period PWMP PWM OUTPUTS ...
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Preliminary Technical Data S/PDIF Transmitter Serial data input to the S/PDIF transmitter can be formatted as 2 left justified right justified with word widths of 16-, 18-, 20-, or 24-bits. The following sections provide timing for the ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 S/PDIF Transmitter Input Data Timing The timing requirements for the S/PDIF transmitter are given in Table 40. Input signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifica- tions provided below are ...
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Preliminary Technical Data S/PDIF Receiver The following section describes timing as it relates to the S/PDIF receiver. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the TBD × FS clock. Table ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 SPI Interface—Master The ADSP-2146x contains two SPI ports. Both primary and sec- ondary are available through DPI only. The timing provided in Table 43 and Table 44 applies to both. Table 43. SPI Interface Protocol—Master Switching and Timing Specifications ...
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Preliminary Technical Data SPI Interface—Slave Table 44. SPI Interface Protocol—Slave Switching and Timing Specifications Parameter Timing Requirements t Serial Clock Cycle SPICLKS t Serial Clock High Period SPICHS t Serial Clock Low Period SPICLS t SPIDS Assertion to First SPICLK ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing Figure 36 describes UART port receive and transmit operations. The maximum baud rate is PCLK/16 where PCLK = 1/tPCLK. As shown in Figure 36 there is some latency between the gener- ...
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Preliminary Technical Data TWI Controller Timing Table 46 and Figure 37 provide timing information for the TWI interface. Input Signals (SCL, SDA) are routed to the DPI_P14–1 pins using the SRU. Therefore, the timing specifica- tions provided below are valid ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 JTAG Test Access Port and Emulation Table 47. JTAG Test Access Port and Emulation Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP 1 t ...
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Preliminary Technical Data Thermal Diode TBD Media Local Bus TBD ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Rev. PrC | Page January 2009 ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 OUTPUT DRIVE CURRENTS Figure 39 shows typical I-V characteristics for the output driv- ers of the ADSP-2146x. The curves represent the current drive capability of the output drivers as a function of output voltage TBD 6 ...
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Preliminary Technical Data TBD 100 150 Figure 44. Typical Output Delay or Hold vs. Load Capacitance (at Ambient Temperature) THERMAL CHARACTERISTICS The ADSP-2146x processor is rated for performance over the temperature ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 BALL CONFIGURATION - ADSP-21462W/ADSP-21465W/ADSP-21469W A1 CORNER INDEX AREA Figure 45. ADSP-21462W/ADSP-21465W/ADSP-21469W Ball Configuration – Pin Out ...
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Preliminary Technical Data PBGA PINOUT – ADSP-21462W/ADSP-21465W/ADSP-21469W Table 49 PBGA Pin Assignment (Alphabetically by Signal) Signal Ball AMI_ACK R10 AMI_ADDR0 V16 AMI_ADDR01 U16 AMI_ADDR02 T16 AMI_ADDR03 R16 AMI_ADDR04 V15 AMI_ADDR05 U15 AMI_ADDR06 T15 AMI_ADDR07 R15 ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Table 49 PBGA Pin Assignment (Alphabetically by Signal) (Continued) Signal Ball V D18 DDR V E02 DDR V E04 DDR V E07 ...
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Preliminary Technical Data BALL CONFIGURATION - ADSP-21467/ADSP-21469 A1 CORNER INDEX AREA ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 PBGA PINOUT - ADSP-21467/ADSP-21469 Table 50 PBGA Pin Assignment (Alphabetically by Signal) Signal Ball AMI_ACK R10 AMI_ADDR0 V16 AMI_ADDR01 U16 AMI_ADDR02 T16 AMI_ADDR03 R16 AMI_ADDR04 V15 AMI_ADDR05 U15 AMI_ADDR06 T15 AMI_ADDR07 R15 AMI_ADDR08 V14 ...
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Preliminary Technical Data Table 50 PBGA Pin Assignment (Alphabetically by Signal) (Continued) Signal Ball V D18 DDR V E02 DDR V E04 DDR V E07 _ ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 OUTLINE DIMENSIONS The ADSP-2146x processors are available PBGA lead-free package. BALL A1 PAD CORNER 2.40 2.28 2.16 19.20 19.00 SQ 18.80 17.00 17.05 BSC SQ 16.95 SQ 16.85 1.00 BSC TOP VIEW ...
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Preliminary Technical Data AUTOMOTIVE PRODUCTS The ADSP-21462W, ADSP-21465W, and ADSP-21469W are available for automotive applications with controlled manufac- turing. Note that these special models may have specifications that differ from the general release models. Table 51. Automotive Products 1 Model ...
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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07809-0-1/09(PrC) Rev. PrC | Page January 2009 Preliminary Technical Data ...