Z8F08200100KITG Zilog, Z8F08200100KITG Datasheet - Page 136

• Manufacturer Part Number: Z8F08200100KITG
• Description: DEV KIT FOR Z8 ENCORE 8K/4K
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F08200100KITG

• Contents: Evaluation Board, Cable, Power Supply, Software and Documentation
• Silicon Manufacturer: Zilog
• Core Architecture: Z8 Encore
• Silicon Core Number: Z8F0822SJ020
• Silicon Family Name: XP F0822
• Rohs Compliant: Yes
• For Use With/related Products: Z8 Encore!™
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4630

Table 65. SPI Status Register (SPISTAT)
PS022517-0508
BITS
FIELD
RESET
R/W
ADDR
R/W* = Read access. Write a 1 to clear the bit to 0.
SPI Status Register
IRQ
7
The SPI Status Register indicates the current state of the SPI. All bits revert to their reset
state if the
IRQ—Interrupt Request
If SPIEN = 1, this bit is set if the STR bit in the SPICTL Register is set, or upon comple-
tion of an SPI Master or Slave transaction. This bit does not set if SPIEN = 0 and the SPI
Baud Rate Generator is used as a timer to generate the SPI interrupt.
0 = No SPI interrupt request pending.
1 = SPI interrupt request is pending.
OVR—Overrun
0 = An overrun error has not occurred.
1 = An overrun error has been detected.
COL—Collision
0 = A multi-master collision (mode fault) has not occurred.
1 = A multi-master collision (mode fault) has been detected.
ABT—SLAVE mode transaction abort
This bit is set if the SPI is configured in SLAVE mode, a transaction is occurring and SS
deasserts before all bits of a character have been transferred as defined by the NUMBITS
field of the SPIMODE Register. The IRQ bit also sets, indicating the transaction has
completed.
0 = A SLAVE mode transaction abort has not occurred.
1 = A SLAVE mode transaction abort has been detected.
Reserved—Must be 0
TXST—Transmit Status
0 = No data transmission currently in progress.
1 = Data transmission currently in progress.
SLAS—Slave Select
If SPI enabled as a Slave
0 = SS input pin is asserted (Low)
1 = SS input is not asserted (High).
If SPI enabled as a Master, this bit is not applicable.
OVR
SPIEN
6
R/W*
bit in the SPICTL Register equals 0.
COL
5
ABT
4
0
F62H
3
Reserved
Z8 Encore! XP
2
Product Specification
R
Serial Peripheral Interface
TXST
1
®
F0822 Series
SLAS
0
1
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