Z8F08200100KITG Zilog, Z8F08200100KITG Datasheet - Page 219

DEV KIT FOR Z8 ENCORE 8K/4K

Z8F08200100KITG

Manufacturer Part Number
Z8F08200100KITG
Description
DEV KIT FOR Z8 ENCORE 8K/4K
Manufacturer
Zilog
Series
Z8 Encore!®r
Type
MCUr

Specifications of Z8F08200100KITG

Contents
Evaluation Board, Cable, Power Supply, Software and Documentation
Silicon Manufacturer
Zilog
Core Architecture
Z8 Encore
Silicon Core Number
Z8F0822SJ020
Silicon Family Name
XP F0822
Rohs Compliant
Yes
For Use With/related Products
Z8 Encore!™
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4630
PS022517-0508
(Output)
(Input)
(Output)
CTS
DE
TXD
Table 111. UART Timing with CTS
Parameter Abbreviation
T
T
T
UART Timing
1
2
3
Figure 54
Clear To Send input pin (CTS) is used for flow control. In this example, it is assumed that
the Driver Enable polarity has been configured to be Active Low and is represented here
by DE. The CTS to DE assertion delay (T1) assumes the UART Transmit Data Register
has been loaded with data prior to CTS assertion.
T
CTS Fall to DE Assertion Delay
DE Assertion to TXD Falling Edge (Start)
Delay
End of Stop Bit(s) to DE Deassertion Delay
1
and
Table 111
T
2
Figure 54. UART Timing with CTS
Start
provide timing information for UART pins for the case where the
Bit 0
Bit 1
2 * XIN period 2 * XIN period
1 * XIN period 2 * XIN period
1 Bit period
Minimum
Z8 Encore! XP
Bit 7
Delay (ns)
Parity
Product Specification
1 * XIN period
Electrical Characteristics
+ 1 Bit period
1 Bit period +
Maximum
Stop
Stop Bit(s)
®
End of
F0822 Series
T
3
206

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