XE8000EV104 Semtech, XE8000EV104 Datasheet - Page 38
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XE8000EV104
Manufacturer Part Number
XE8000EV104
Description
EVAL BOARD FOR XE8805AMI028LF
Manufacturer
Semtech
Type
MCUr
Specifications of XE8000EV104
Contents
Fully Assembled Evaluation Board
For Use With/related Products
XE88LC05AMI028
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 38 of 156
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Table 6-3. RegSysWD register
6.4 Reset handling capabilities
There are 5 reset sources:
Another reset source is the bit Sleep in the RegSysReset register. This source is fully controlled by software and
is only used during the sleep mode.
Four internal reset signals are generated from these sources and distributed through the system:
For the
Table 6-4 shows a summary of the dependency of the internal reset signals on the various reset sources. In all the
tables describing the different registers, the reset source is indicated.
Table 6-4. Internal reset assertion as a function of the reset source.
© Semtech 2006
7 – 4
Pos.
Asserted
reset source
POR
RESET pin (1)
RESET pin (2)
PortA input
Watchdog
BusError
Sleep
3
2
1
0
(2) For the circuits XE8801 and XE8805
(1) For the circuits XE8801A and XE8805A
(2) For the circuits XE8801 and XE8805
circuits XE8801A and XE8805A
RegSysWD
-
WDKey[3]
WDCounter[3]
WDKey[2]
WDCounter[2]
WDKey[1]
WDCounter[1]
WDKey[0]
WDCounter[0]
• Power On Reset (POR)
• External reset from the RESET pin
• Programmable Port A input combination
• Programmable watchdog timer reset
• Programmable BusError reset on processor access outside the allocated memory map
• resetcold:
• resetsystem: is asserted when resetcold or any other enabled reset source is active
• resetpconf:
• resetsleep:
resetsystem
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
is asserted on POR
is asserted when resetsystem is active and if the
is set. This reset is generally used in the different ports. It allows to maintain the port
configuration unchanged while the rest of the circuit is reset.
is asserted when the circuit is in sleep mode
Rw
r
w
r
w
r
w
r
w
r
-
Reset
0000
0 resetcold
0 resetcold
0 resetcold
0 resetcold
EnResPConf=0
Asserted
Asserted
when
-
-
-
-
-
Function
unused
Watchdog Key bit 3
Watchdog counter bit 3
Watchdog Key bit 2
Watchdog counter bit 2
Watchdog Key bit 1
Watchdog counter bit 1
Watchdog Key bit 0
Watchdog counter bit 0
Internal reset signals
resetpconf
EnResPConf=1
6-3
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
when
-
EnResPConf bit in the
resetsleep
Asserted
Asserted
Asserted
-
-
-
-
resetcold
Asserted
Asserted
XE8805/05A
RegSysCtrl register
-
-
-
-
-
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