DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 49

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices
April 2011 Altera Corporation
Sinusoidal Jitter tolerance at
1536 Mbps
Sinusoidal Jitter tolerance at
3072 Mbps
Notes to
(1) Dedicated refclk pins were used to drive the input reference clocks.
(2) The Jitter numbers are valid for the stated conditions only.
(3) The jitter numbers for SONET/SDH are compliant to the GR-253-CORE Issue 3 Specification.
(4) The jitter numbers for Fibre Channel are compliant to the FC-PI-4 Specification revision 6.10.
(5) The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.
(6) The jitter numbers for PCI Express (PIPE) (PCIe) are compliant to the PCIe Base Specification 2.0.
(7) The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3.
(8) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
(9) The jitter numbers for HiGig are compliant to the IEEE802.3ae-2002 Specification.
(10) The jitter numbers for (OIF) CEI are compliant to the OIF-CEI-02.0 Specification.
(11) The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications.
(12) The fibre channel transmitter jitter generation numbers are compliant to the specification at δ
(13) The fibre channel receiver jitter tolerance numbers are compliant to the specification at δ
(14) You must use the ATX PLL adjacent to the transceiver channels to meet the transmitter jitter generation compliance in PCIe Gen2 ×8 modes.
(15) Stratix IV PCIe receivers are compliant to this specification provided the V
(16) The jitter numbers for Serial Attached SCSI (SAS) are compliant to the SAS-2.1 Specification.
(17) The jitter numbers for CPRI are compliant to the CPRI Specification V3.0.
(18) The jitter numbers for OBSAI are compliant to the OBSAI RP3 Specification V4.1.
Table
Description
Symbol/
1–30:
Jitter Frequency =
10.9 KHz
Pattern = CJPAT
Jitter Frequency =
921.6 MHz to 20 MHz
Pattern = CJPAT
Jitter Frequency = 21.8
KHz
Pattern = CJPAT
Jitter Frequency =
1843.2 MHz to 20 MHz
Pattern = CJPAT
Conditions
Min
–2 Commercial
Speed Grade
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
Typ
> 8.5
> 0.1
> 8.5
> 0.1
TX-CM-DC-ACTIVEIDLE-DELTA
Max
R
interoperability point.
Min
(Note
–2× Commercial
–3 Commercial/
T
Industrial and
Speed Grade
interoperability point.
of the upstream transmitter is less than 50mV.
1),
Typ
> 8.5
> 0.1
> 8.5
> 0.1
(2)
Max
(Part 8 of 8)
Min
Industrial Speed
–4 Commercial/
Typ
Grade
> 8.5
> 0.1
> 8.5
> 0.1
Max
1–41
Unit
UI
UI
UI
UI