DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 52
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
1–44
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
Core Performance Specifications
f
1
Transceiver Datapath PCS Latency
For more information about:
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This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), TriMatrix, configuration, JTAG, and chip-wide reset (Dev_CLRn)
specifications.
Clock Tree Specifications
Table 1–33
Table 1–33. Clock Tree Performance for Stratix IV Devices—Preliminary
For the Stratix IV GT –1 and –2 speed grade specifications, refer to the –2/–2× speed
grade column. For the Stratix IV GT –3 speed grade specification, refer to the –3 speed
grade column.
Global clock and
Regional clock
Periphery clock
Basic mode PCS latency, refer to Figure 1-90 through Figure 1-97 in the
Architecture in Stratix IV Devices
PCIe mode PCS latency, refer to Figure 1-102 in the
Stratix IV Devices
XAUI mode PCS latency, refer to Figure 1-119 in the
Stratix IV Devices
GIGE mode PCS latency, refer to Figure 1-128 in the
Stratix IV Devices
SONET/SDH mode PCS latency, refer to Figure 1-136 in the
Architecture in Stratix IV Devices
SDI mode PCS latency, refer to Figure 1-141 in the
Stratix IV Devices
(OIF) CEI PHY mode PCS latency, refer to Figure 1-143 in the
Architecture in Stratix IV Devices
Symbol
lists the clock tree specifications for Stratix IV devices.
–2/–2× Speed Grade
chapter.
chapter.
chapter.
chapter.
800
550
Performance
chapter.
chapter.
chapter.
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
–3 Speed Grade
700
500
Transceiver Architecture in
Transceiver Architecture in
Transceiver Architecture in
Transceiver Architecture in
–4 Speed Grade
April 2011 Altera Corporation
Transceiver
500
450
Transceiver
Switching Characteristics
Transceiver
Unit
MHz
MHz