45205 Parallax Inc, 45205 Datasheet - Page 167

• Manufacturer Part Number: 45205
• Description: SX TECH BOARD
• Manufacturer: Parallax Inc
• Type: MCUr

Specifications of 45205

• Contents: Board
• For Use With/related Products: SX MCUs
• For Use With: 28825 - MINI SOUND PLAYER SOUNDPAL130-28029 - KIT PARTS SMART SENSORS
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

stack and the special shadow registers for W, STATUS, and the FSR, which were preserved during
interrupt handling. RETIW behaves the same as RETI but also compensates the RTCC by adding the
value in W to the RTCC.
15.3 Port Configuration Registers
15.3.1 Port A Registers
There are three registers used to configure the I/O pins of Port A. The TRIS_A register configures the
data direction of the Port A pins as input or output. The LVL_A register configures the input pins as
TTL or CMOS voltage level. The PLP_A register enables/disables pull up resistors on Port A input pins.
To access these registers you must first write a particular value to the MODE register. Please refer
to
following Port A Registers. Note: All the bits in the following registers are set to ‘1’ on power up.
15.3.1.1
A bit set to ‘1’ in this register sets the corresponding I/O port pin to input (high z) mode.
A bit set to ‘0’ in this register sets the corresponding I/O port pin to output mode.
15.3.1.2
A bit set to ‘1’ in this register sets the input level of the corresponding port pin to TTL.
A bit set to ‘0’ in this register sets the input level of the corresponding port pin to CMOS.
15.3.1.3
A bit set to ‘1’ in this register disables the weak pull-up resistor on the corresponding port pin. A bit set
to ‘0’ in this register enables the weak pull-up resistor on the corresponding port pin.
Table
32 – SX20/28 Mode Register to find the values required in the MODE register to access the
TRIS_A – Data Direction Register
LVL_A - TTL/CMOS Select Register
PLP_A – Pull-Up Resistor Enable Register
7
7
7
-
-
-
6
6
6
-
-
-
5
5
5
-
-
-
SX-Key/Blitz Development System Manual 2.0 Parallax, Inc. Page 167
TRIS_A
4
4
4
LVL_A
PLP_A
-
-
-
RA3 RA2 RA1 RA0
RA3 RA2 RA1 RA0
RA3 RA2 RA1 RA0
3
3
3
15 Appendix E: SX Data Sheet
2
2
2
1
1
1
0
0
0