Z8F083A0128ZCOG Zilog, Z8F083A0128ZCOG Datasheet - Page 11

• Manufacturer Part Number: Z8F083A0128ZCOG
• Description: KIT DEVELOPMENT F083A
• Manufacturer: Zilog
• Series: Z8 Encore! XP®r
• Type: MCUr

Specifications of Z8F083A0128ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F083A
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4672

PRS001003-1207
Notes:
1. During read operation, PROG, SERA, MASE, and NVSTR are always logic "L".
2. IFREN pin determines whether the macros, CE and AE must be asserted; otherwise
3. To enable the macro, CE and AE must be asserted; otherwise macro will ignore any
4. For continuous read, Address and IFREN are allowed to be in transition.
5. In order to access information block, ADDR[13:7] are don’t care. ADDR[6:0] are
6. Reading operation starts from AE rising edge. Prior to AE’s rising edge; CE, OE,
7. All input waveforms are with rising time (tr) and falling time (tf) of 1 ns. The capacitor
8. Access time (Tae) is measured with 0.1 pF load capacitance.
9. Tdf refers to data hold time from the end of Tcyc. Output data will not be valid after
macro will ignore any change from control pins and address.
change from control pins and address.
used to select one column in each I/O within the information block.
ADDR must be valid.
loading for the eFlash macro input pin is 0.5 pF.
Tdf.
Z8 Encore!
®
F083x Series
Page 11 of 25