Z8F083A0128ZCOG Zilog, Z8F083A0128ZCOG Datasheet
Z8F083A0128ZCOG
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... High-Performance 8-Bit Microcontrollers ® Z8 Encore! F083A Series Product Specification PS026308-1207 Copyright © 2007 by Zilog ® , Inc. All rights reserved. www.zilog.com ...
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... TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, and ZNEO are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. PS026308-1207 ...
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Revision History Each instance in the Revision History of this document reflects a change to this document from its previous revision. For more details, refer to the corresponding pages or appropriate links given in the table below. Revision Date Level ...
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PS026308-1207 ® Z8 Encore! F083A Series Product Specification iv ...
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Table of Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Watchdog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ADC Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Trim Bit Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Flash Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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PS026308-1207 ® Z8 Encore! F083A Series Product Specification Table of Contents xii ...
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... PS026308-1207 ® MCU family of products are the first in a line of Zilog ® Z8 Encore! F083A Series Product Specification ® CPU instructions. The ...
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Part selection guide Table 1 lists the basic features available for each device within the Z8 Encore! F083A Series product line. For details, see Table 1. Z8 Encore! F083A Series Family Part Selection Guide Part Flash Number (KB) Z8F083A Z8F043A ...
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CPU Memory Bus Register Bus Timers Comparator GPIO Figure 1. Z8 Encore! F083A Series Block Diagram PS026308-1207 System Oscillator Clock Control On-Chip Debugger Interrupt Controller NVDS ADC Controller ® Z8 Encore! F083A Series Product Specification XTAL/RC Oscillator Internal Precision ...
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... CPU and Peripheral Overview eZ8 CPU Features The eZ8 CPU, Zilog’s latest 8-bit CPU, meets the continuing demand for faster and more code-efficient microcontrollers. The eZ8 CPU executes a superset of the original Z8 instruction set. The eZ8 CPU features include: • Direct register-to-register architecture allows each register to function as an accumulator, improving execution time and decreasing the required program memory. • ...
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Non Volatile Data Storage The non volatile data storage (NVDS) uses a hybrid hardware/software scheme to implement a byte programmable data memory and is capable of storing about 100,000 write cycles. Internal Precision Oscillator The internal precision oscillator (IPO) with ...
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Reset Controller The Z8 Encore! F083A Series products are reset using any one of the following: the RESET pin, POR, WDT timeout, STOP mode exit, or VBO warning signal. The RESET pin is bidirectional, that is, it functions as reset ...
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Pin Description The Z8 Encore! F083A Series products are available in variety of package styles and pin configurations. This chapter describes the signals and the pin configurations for each of the package styles. For information on the physical package specifications, ...
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PB2/ANA2 PB4/ANA7 PB5/VREF PB3/CLKIN/ANA3 PA0/T0IN/T0OUT/XIN PA1/T0OUT/XOUT Figure 3. Z8F083A Series in 28-Pin SOIC and SSOP Packages PS026308-1207 PB1/ANA1 1 28 PB0/ANA0 PC3/COUT/LED PC2/ANA6/LED 4 25 AVDD PC1/ANA5/CINN/LED PC0/ANA4/CINP/LED VDD 7 22 DBG ...
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PC3/COUT/LED 16 PB0/ANA0 17 PB1/ANA1 18 PB2/ANA2 19 PB3/CLKIN/ANA3 20 Figure 4. Z8F083A Series in 20-Pin QFN Package PS026308-1207 PA7/T1OUT 10 PA6/T1IN/T1OUT 9 PA5 8 20-Pin QFN PA4 7 PA3 ...
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PC3/COUT/LED PB0/ANA0 PB1/ANA1 PB2/ANA2 PB4/ANA7 PB5/VREF PB3/CLKIN/ANA3 Figure 5. Z8F083A Series in 28-Pin QFN Package Signal Descriptions Table 3 on page 11 describes the Z8 Encore! F083A Series signals. To determine the signals available for the specific package styles, see ...
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Table 3. Signal Descriptions Signal Mnemonic I/O Description General-Purpose Input/Output Ports A–D PA[7:0] I/O Port A. These pins are used for GPIO. PB[5:0] I/O Port B. These pins are used for GPIO. PC[7:0] I/O Port C. These pins are used ...
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Table 3. Signal Descriptions (Continued) Signal Mnemonic I/O Description LED O Direct LED drive capability. All Port C pins have the capability to drive an LED without any other external components. These pins have programmable drive strengths set by the ...
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Table 4. Pin Characteristics (20- and 28-pin Devices) (Continued) Symbol Reset Mnemonic Direction Direction PA[7:0] I/O I PB[5:0] I/O I PC[7:0] I/O I RESET/PD0 I/O I/O (defaults to RESET) VDD N/A N/A VSS N/A N/A PS026308-1207 Active Low or Internal ...
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PS026308-1207 ® Z8 Encore! F083A Series Product Specification Pin Description 14 ...
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... The following sections describe about these three address spaces. For more detailed information on the eZ8 CPU and its address space, refer to eZ8 CPU User Manual available for download at www.zilog.com. Register File The Register File address space in the Z8 Encore! MCU (4096 bytes). The Register File consists of two sections: control registers and general purpose registers ...
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Flash memory addresses returns program memory addresses produces no effect. maps for the Z8 Encore! F083A Series products. Table 5. Z8 Encore! F083A Series Program Memory Maps Program Memory Address (Hex) Z8F083A Products 0000–0001 0002–0003 0004–003D 003E–1FFF Z8F043A ...
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... Program Memory Address (Hex) FE00–FE3F FE40–FE53 FE54–FE5F FE60–FE7F FE80–FFFF PS026308-1207 ® Z8 Encore! Product Specification Function Zilog option bits Part Number 20-character ASCII alphanumeric code Left justified and filled with FH Reserved Zilog calibration data Reserved F083A Series 17 Address Space ...
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PS026308-1207 ® Z8 Encore! F083A Series Product Specification Address Space 18 ...
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Register Map Table 7 provides the address map for the register file of the Z8 Encore! F083A Series devices. Consider registers for unimplemented peripherals as reserved. Table 7. Register File Address Map Address (Hex) Register Description General Purpose RAM 000–0FF ...
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Table 7. Register File Address Map (Continued) Address (Hex) Register Description F75 ADC sample time F76 ADC Clock Prescale F77–F7F Reserved Low Power Control F80 Power control 0 F81 Reserved LED Controller F82 LED drive enable F83 LED drive level ...
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Table 7. Register File Address Map (Continued) Address (Hex) Register Description FD2 Port A input data FD3 Port A output data GPIO Port B FD4 Port B address FD5 Port B control FD6 Port B input data FD7 Port B ...
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Table 7. Register File Address Map (Continued) Address (Hex) Register Description FFB Flash programming frequency low byte eZ8 CPU FFC Flags FFD Register pointer FFE Stack pointer high byte FFF Stack pointer low byte XX=Undefined PS026308-1207 ® Z8 Encore! F083A ...
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Reset and Stop Mode Recovery The reset controller in the Z8 Encore! F083A Series controls Reset and Stop Mode Recovery operations typical operation, the following events cause a Reset: • Power-On Reset • Voltage Brownout • Watchdog Timer ...
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Table 8. Reset and Stop Mode Recovery Characteristics and Latency (Continued) Reset Type Control Registers Stop Mode Recovery Unaffected, except WDT_CTL and OSC_CTL registers Stop Mode Recovery with Unaffected, except crystal oscillator enabled WDT_CTL and OSC_CTL registers During a system ...
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Reset Sources Table 9 lists the possible sources of a system reset. Table 9. Reset Sources and Resulting Reset Type Operating Mode Reset Source NORMAL or HALT Power-On Reset / Voltage modes Brownout WDT time-out when configured for reset RESET ...
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V POR V VBO VDD = 0.0V Internal Precision Oscillator Crystal Oscillator Internal RESET signal Note: Not to Scale Voltage Brownout Reset The devices in the Z8 Encore! F083A Series provide low VBO protection. The VBO circuit forces the device ...
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VDD = 3 POR V VBO Program Execution WDT Clock System Clock Internal RESET signal Note: Not to Scale Figure 7. Voltage Brown-Out Reset Operation Watchdog Timer Reset If the device is in NORMAL or STOP mode, the ...
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Reset state on the system clock rising edge following RESET pin deassertion. Following a system reset initiated by the external RESET pin, the EXT status bit in the reset status (RSTSTAT) register is set to 1. External ...
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Table 10. Stop Mode Recovery Sources and Resulting Action Operating Mode Stop Mode Recovery Source STOP mode WDT time-out when configured for Reset WDT time-out when configured for interrupt Data transition on any GPIO port pin enabled as a Stop ...
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Debug Pin Driven Low Debug reset is initiated when the On-Chip Debugger detects any of the following error conditions on the DBG pin: • Serial break (a minimum of nine continuous bits low) • Framing error (received STOP bit is ...
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POR—Power-On Reset indicator This bit is set POR event occurs and is reset WDT time-out or Stop Mode Recovery occurs. Reading this register also resets this bit to 0. STOP—Stop Mode Recovery ...
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PS026308-1207 ® Z8 Encore! F083A Series Product Specification Reset and Stop Mode Recovery 32 ...
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Low-Power Modes The Z8 Encore! F083A Series products contain power saving features. The highest level of power reduction is provided by the STOP mode. The next level of power reduction is provided by the HALT mode. Further power savings are ...
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HALT Mode Executing the eZ8 CPU HALT instruction places the device into HALT mode. In HALT mode, the operating characteristics are: • Primary oscillator is enabled and continues to operate. • System clock is enabled and continues to operate. • ...
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This register is only reset during a POR sequence. Other system Reset events do not affect Note: it. Table 12. Power Control Register 0 (PWRCTL0) BITS 7 6 Reserved FIELD 1 0 RESET R/W R/W R/W ADDR Reserved—Must be 0. ...
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PS026308-1207 ® Z8 Encore! F083A Series Product Specification Low-Power Modes 36 ...
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General Purpose Input/Output The Z8 Encore! F083A Series products support a maximum of 23 port pins (Port A–D) for general purpose input/output (GPIO) operations. Each port contains control and data registers. The GPIO control registers determine data direction, open-drain, output ...
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System Port Output Data Register DATA D Q Bus System Clock Figure 8. GPIO Port Pin Block Diagram GPIO Alternate Functions Many of the GPIO port pins are used for general purpose input/output and access to on- chip peripheral functions ...
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Direct LED Drive The Port C pins provide a sinked current output, capable of driving an LED without requiring an external resistor. The output sinks current at programmable levels of 3 mA, 7 mA, 13 mA, and 20 mA. This ...
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External Clock Setup For systems using an external TTL drive, PB3 is the clock source for 20- and 28-pin devices. In this case, configure PB3 for alternate function CLKIN. Write to the oscillator control register (see page 148) to select ...
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Table 14. Port Alternate Function Mapping (Continued) Port Pin Mnemonic PB0 Reserved B ANA0 PB1 Reserved ANA1 PB2 Reserved ANA2 PB3 CLKIN ANA3 PB4 Reserved ANA7 PB5 Reserved VREF PB6 Reserved Reserved PB7 Reserved Reserved PS026308-1207 Z8 Encore! Alternate Function ...
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Table 14. Port Alternate Function Mapping (Continued) Port Pin Mnemonic PC0 Reserved C ANA4/CINP/LED Drive PC1 Reserved ANA5/CINN/ LED Drive PC2 Reserved ANA6/LED PC3 COUT LED PC4 Reserved LED PC5 Reserved LED PC6 Reserved LED PC7 Reserved LED D PD0 ...
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GPIO Control Register Definitions Four registers for each port provide access to GPIO control, input data, and output data. Table 15 lists these port registers. Use the Port A–D address and control registers together to provide access to subregisters for ...
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Port A–D Address Registers The Port A–D address registers select the GPIO port functionality accessible through the Port A–D control registers. The Port A–D address and control registers combine to provide access to all GPIO port controls (see Table 16. ...
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Table 17. Port A–D Control Registers (PxCTL) BITS 7 6 FIELD RESET R/W R/W R/W ADDR PCTL[7:0]—Port Control The port control register provides access to all subregisters that configure the GPIO port operation. Port A–D Data Direction Subregisters The Port ...
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Subregisters on page 49 pin, see GPIO Alternate Functions Caution: Do not enable alternate functions for GPIO port pins for which there is no associated alternate function. Failure to follow this guideline results in unpredictable operation. Table 19. Port A–D ...
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The drains are enabled for any output mode (unless overridden by the alternate function The drain of the associated pin is disabled (OPEN-DRAIN mode). Port A–D High Drive Enable Subregisters The Port A–D high drive enable ...
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PSMRE[7:0]—Port Stop Mode Recovery source enabled 0 = The port pin is not configured as a Stop Mode Recovery source. Transitions on this pin during STOP mode do not initiate Stop Mode Recovery The port pin is configured ...
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Table 24. Port A–D Alternate Function Set 1 Subregisters (PxAFS1) BITS 7 6 PAFS17 PAFS16 FIELD 0 0 RESET R/W R/W R/W If 07H in Port A–D Address Register, accessible through the Port A–D Control Register ADDR PAFS1[7:0]—Port alternate function ...
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Port A–C Input Data Registers Reading from the Port A–C input data registers, returns the sampled values from the corresponding port pins. See read-only. The value returned for any unused ports is 0. Unused ports include those missing on the ...
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LED Drive Enable Register The LED drive enable register activates the controlled current drive. See Port C pin must first be enabled by setting the alternate function register to select the LED function. See Table 14 . Table 28. LED ...
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LED Drive Level Low Register The LED drive level registers contain two control bits for each Port C pin. See These two bits selects one of four programmable current drive levels for each Port C pin. Each pin is individually ...
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... The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts, the interrupt controller has no effect on operation. For more information regarding interrupt servicing by the eZ8 CPU, refer to eZ8 CPU User Manual. The eZ8 CPU User Manual is available for download at www.zilog.com. Interrupt Vector Listing Table 31 on page 54 lists the interrupts available in order of priority ...
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Table 31. Trap and Interrupt Vectors in Order of Priority Program Memory Priority Vector Address Interrupt or Trap Source Highest 0002H Reset (not an interrupt) 0004H Watchdog Timer (see Watchdog Timer chapter) 003AH Primary oscillator fail trap (not an interrupt) ...
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Table 31. Trap and Interrupt Vectors in Order of Priority (Continued) Program Memory Priority Vector Address Interrupt or Trap Source Lowest 0036H Port C0, both input edges 0038H Reserved Architecture Figure 9 displays the interrupt controller block diagram. Port Interrupts ...
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Execution of an IRET (return from interrupt) instruction • Writing 1 to the IRQE bit in the interrupt control register Interrupts are globally disabled by any of the following actions: • Execution (disable interrupt) instruction • ...
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AND r0, MASK LDX IRQ0, r0 Caution: To avoid missing interrupts, use the following coding style to clear bits in the interrupt request 0 register: Good coding style that avoids lost interrupt requests: ANDX IRQ0, MASK Software Interrupt Assertion Program ...
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CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU reads the interrupt request 0 register to determine if any interrupt requests are pending. Table 32. Interrupt Request 0 Register (IRQ0) BITS 7 6 Reserved T1I FIELD 0 0 ...
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PA7I—Port interrupt request is pending for GPIO Port interrupt request from GPIO Port A. PA6CI—Port A6 or comparator interrupt request interrupt request is pending for GPIO Port A or ...
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Priority is generated by setting bits in each register. Table 35. IRQ0 Enable and Priority Encoding IRQ0ENH[x] IRQ0ENL[x] Priority where x indicates the register bits from 0–7. Table 36. ...
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IRQ1 Enable High and Low Bit Registers Table 38 describes the priority control for IRQ1. The IRQ1 enable high and low bit registers (Table 39 interrupt request 1 register. Priority is generated by setting bits in each register. Table 38. ...
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PA7ENH—Port A Bit[7] interrupt request enable low bit PA6CENH—Port A Bit[6] or comparator interrupt request enable low bit PAxENL—Port A Bit[x] interrupt request enable low bit IRQ2 Enable High and Low Bit Registers Table 41 describes the priority control for ...
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Table 43. IRQ2 Enable Low Bit Register (IRQ2ENL) BITS 7 6 Reserved FIELD 0 0 RESET R/W R/W R/W ADDR Reserved—Must be 0. C3ENL—Port C3 interrupt request enable low bit C2ENL—Port C2 interrupt request enable low bit C1ENL—Port C1 interrupt ...
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Because these shared interrupts are edge-triggered possible to generate an interrupt just by switching from one shared source to another. For this reason, an interrupt must be disabled before switching between sources. Table 45. Shared Interrupt Select Register ...
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Timers The Z8 Encore! F083A Series products contain up to two 16-bit reloadable timers that are used for timing, event counting, or generation of pulse width modulated (PWM) signals. The timers features include: • 16-bit reload counter. • Programmable prescaler ...
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Data Bus Block Control System Clock Timer Input Gate Input Capture Input Operation The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value into the timer reload high and low byte registers and setting the prescale ...
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ONE-SHOT time-out (rather than a single cycle pulse), first set the TPOL bit in the timer control register to the start value before enabling ONE-SHOT mode. After starting the timer, set ...
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If using the timer output alternate function, set the initial output level (high or – low) 2. Write to the timer high and low byte registers to set the starting count value (usually 0001H). This action only affects the first ...
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Select either the rising edge or falling edge of the timer input signal for the count. – This selection also sets the initial logic level (high or low) for the timer output alternate function. However, the timer output function is ...
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Select either the rising edge or falling edge of the comparator output signal for the – count. This also sets the initial logic level (high or low) for the timer output alternate function. However, the timer output function is not ...
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The steps for configuring a timer for PWM SINGLE OUTPUT mode and for initiating the PWM operation are as follows: 1. Write to the timer control register to: Disable the timer – Configure the timer for PWM mode – Set ...
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PWM DUAL OUTPUT Mode In PWM DUAL OUTPUT mode, the timer outputs a PWM output signal pair (basic PWM signal and its complement) through two GPIO port pins. The timer input is the system clock. The timer first counts up ...
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PWM signal (as defined by the difference between the PWM registers and the timer reload registers). 5. Write to the timer reload high and low byte registers to set the reload value (PWM ...
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The timer continues counting up to the 16-bit reload value stored in the timer reload high and low byte registers. On reaching the reload value, the timer generates an interrupt and continues counting. The INPCAP bit in TxCTL1 register clears, ...
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The INPCAP bit in TxCTL1 register is set to indicate, the timer interrupt is caused by an input Capture event Capture event occurs, the timer counts up to 16-bit compare value stored in the timer ...
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COMPARE Mode In COMPARE mode, the timer counts up to 16-bit maximum compare value stored in the timer reload high and low byte registers. The timer input is the system clock. On reaching the compare value, the timer generates an ...
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The steps for configuring a timer for GATED mode and for initiating the count are ...
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The steps for configuring a timer for CAPTURE/COMPARE mode and for initiating the count are as follows: 1. Write to the timer control register to: Disable the timer – Configure the timer for CAPTURE/COMPARE mode – Set the prescale value ...
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The timer input is used as a selectable counting source. It shares the same pin as the complementary timer output. When selected by the GPIO alternate function registers, this pin functions as a timer input in all modes except for ...
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Timer Reload High and Low Byte Registers The timer 0–1 reload high and low byte (TxRH and TxRL) registers Table 50) store a 16-bit reload value, {TRH[7:0], TRL[7:0]}. Values written to the timer reload high byte register are stored in ...
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Table 51. Timer 0–1 PWM High Byte Register (TxPWMH) BITS 7 6 FIELD 0 0 RESET R/W R/W R/W ADDR Table 52. Timer 0–1 PWM Low Byte Register (TxPWML) BITS 7 6 FIELD 0 0 RESET R/W R/W R/W ADDR ...
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TMODEHI—Timer mode high bit This bit along with the TMODE field in TxCTL1 register determines the operating mode of the timer. This is the most significant bit of the timer mode selection value. For more details, see Timer 0–1 Control ...
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TEN—Timer enable 0 = Timer is disabled Timer enabled to count. TPOL—Timer input/output polarity Operation of this bit is a function of the current operating mode of the timer. ONE-SHOT Mode When the timer is disabled, the timer ...
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PWM DUAL OUTPUT Mode 0 = Timer output is forced low (0) and timer output complement is forced high (1), when the timer is disabled. When enabled and the PWM count matches, the timer output is forced high (1) and ...
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TMODE—TIMER mode This field along with the TMODEHI bit in TxCTL0 register determines the operating mode of the timer. TMODEHI is the most significant bit of the timer mode selection value. • 0000 = ONE-SHOT mode • 0001 = CONTINUOUS ...
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PS026308-1207 ® Z8 Encore! F083A Series Product Specification Timers 86 ...
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Watchdog Timer The Watchdog Timer (WDT) protects from corrupted or unreliable software, power faults, and other system-level problems, which may place the Z8 Encore! F083A Series devices into unsuitable operating states. The Watchdog Timer includes the following features: • On-chip ...
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Table 55. Watchdog Timer Approximate Time-Out Delays WDT Reload Value WDT Reload Value (Hex) (Decimal) 000004 000400 FFFFFF 16,777,215 Watchdog Timer Refresh On first enable, the Watchdog Timer is loaded with the value in the WDT reload registers. The Watchdog ...
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WDT Interrupt in STOP Mode If configured to generate an interrupt when a time-out occurs and the Z8 Encore! F083A Series devices are in STOP mode, the Watchdog Timer automatically initiates a Stop Mode Recovery and generates an interrupt request. ...
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The value in the Watchdog Timer reload registers is loaded into the counter when the Watchdog Timer is first enabled and every time a ...
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Table 57. Watchdog Timer Reload Upper Byte Register (WDTU) BITS 7 6 FIELD 0 0 RESET R/W* R/W* R/W ADDR R/W* - Read returns the current WDT count value. Write sets the appropriate reload value. WDTU—WDT reload upper byte MSB, ...
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PS026308-1207 ® Z8 Encore! F083A Series Product Specification Watchdog Timer 92 ...
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Analog-to-Digital Converter The Z8 Encore! includes an eight-channel Successive Approximation Register (SAR) analog-to-digital converter (ADC). The ADC converts an analog input signal to a 10-bit binary number. The features of the SAR ADC include: • Eight analog input sources multiplexed ...
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Internal Voltage Reference Generator Analog-to-Digital Converter Reference Input 10 Data Output Analog Input BUSY ADCLK ADCEN START Figure 11. Analog-to-Digital Converter Block Diagram Operation The ADC converts the analog input, ANA equation for calculating the digital value is represented by: ...
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ADC Timing Each ADC measurement consists of three phases: 1. Input sampling (programmable, minimum of 1.0 µs). 2. Sample-and-hold amplifier settling (programmable, minimum of 0.5 µs). 3. Conversion is 13 ADCLK cycles. Figure 12 displays the timing of an ADC ...
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ADC Interrupt The ADC generates an interrupt request when a conversion has been completed. An interrupt request that is pending when the ADC is disabled is not cleared automatically. Reference Buffer The reference buffer, RBUF, supplies the reference voltage for ...
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Bit Value Description Position (H) [7] ADC Start/Busy START 0 Writing to 0 has no effect. Reading a 0 indicates that the ADC is available to begin a conversion. 1 Writing to 1 starts a conversion. Reading a 1 indicates ...
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Table 61. ADC Data High Byte Register (ADCD_H) BITS 7 6 FIELD RESET R/W ADDR Bit Value Description Position (H) [7:0] 00h–FFh ADC high byte The last conversion output is held in the data registers until the next ADC conversion ...
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Sample Settling Time Register The sample settling time register, listed in SAMPLE/HOLD signal is asserted before the START signal is asserted, which begins the conversion. The number of clock cycles required for settling will vary from system to system depending ...
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Sample Time Register The sample time register, listed in for the sample after a conversion has begun by setting the START bit in the ADC control register. The number of system clock cycles required for the sample time varies from ...
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ADC Clock Prescale Register The ADC clock prescale register, listed in clock to the ADC. When this register is programmed with the ADC clock. DIV8 has the highest priority, DIV2 has the lowest priority. Table 65. ADC Clock Prescale Register ...
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PS026308-1207 ® Z8 Encore! F083A Series Product Specification Analog-to-Digital Converter 102 ...
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Comparator The Z8 Encore! F083A Series devices feature a general purpose comparator that compares two analog input signals. A GPIO ( negative input ( CINN reference. The output is available as an interrupt source or is routed to an external ...
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Table 66. Comparator Control Register (CMP0) BITS 7 6 Reserved INNSEL FIELD 0 0 RESET R/W R/W R/W ADDR Reserved GPIO pin always used as positive comparator input INNSEL—Signal select for negative input 0 = internal reference disabled, GPIO pin ...
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Flash Memory The products in the Z8 Encore! F083A Series features either 4 KB (4096 bytes with NVDS (8192 bytes with NVDS) of non volatile Flash memory with read/write/ erase capability. The Flash memory is programmed and ...
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Sector 7 0E00H 0DFFH Sector 6 0C00H 0BFFH Sector 5 0A00H 09FFH Sector 4 0800H 07FFH Sector 3 0600H 05FFH Sector 2 0400H 03FFH Sector 1 0200H 01FFH Sector 0 0000H PS026308-1207 Figure 14. 4K Flash with NVDS ® ...
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... Data Memory Address Space The Flash information area, including the Zilog Flash option bits, are located in the data memory address space. The Z8 Encore! is configured by the Zilog Flash option bits to prevent you from writing to the eZ8 CPU data memory address space. Flash Information Area ...
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... The trim bits are handled differently than the other Zilog Flash option bits. The trim bits are the hybrid of the user option bits and the standard Zilog option bits. These trim bits must be user accessible for reading at all times using external registers, regardless of the state of bit 7 in the Flash page select register ...
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Reset Lock State 0 Write Page Select Register Write FCTL No 73H Yes Lock State 1 Write FCTL No 8CH Yes Write Page Select Register No Page Select values match? Yes Yes Page in Protected Sector? No Page Unlocked Program/Erase ...
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Flash Operation Timing Using the Flash Frequency Registers Before performing either a Program or Erase operation on Flash memory, you must first configure the Flash frequency high and low byte registers. The Flash frequency registers allow programming and erasing of ...
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Code Protection using Flash Controller Table 69. Flash Code Protection using the Flash Option Bits FHSWP FWP reset, the Flash controller is locked to prevent accidental program or erasure of the Flash ...
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... CPU execution of the LDC or LDCI instructions. For the description of the LDC and LDCI instructions, refer to eZ8 CPU User Manual (available for download at www.zilog.com). While the Flash controller programs the Flash memory, the eZ8 CPU idles, but the system clock and on-chip peripherals continue to operate. To exit programming mode and lock the Flash, write any value to the Flash control register, except the mass erase or page erase commands ...
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... The device uses Flash memory, despite the maximum specified Flash size (except 12 KB mode with non-NVDS). User code accesses the lower flash, leaving the upper 4 K for Zilog memory. The NVDS is implemented by using Zilog memory for special purpose routines and for the data required by the routines. These ...
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... See The NVDS routines are triggered by a user code: CALL into Zilog memory. Code executing from Zilog memory must be able to read and write other locations within Zilog memory. User code must not be able to read or write Zilog memory. Flash Control Register Definitions ...
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Table 71. Flash Status Register (FSTAT) BITS 7 6 Reserved FIELD 0 0 RESET R R R/W ADDR Reserved—Must be 0. FSTAT—Flash controller status 000000 = Flash controller locked 000001 = First unlock command received (73H written) 000010 = Second ...
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INFO_EN—Information area enable 0 = Information area is not selected 1 = Information area is selected. The information area is mapped into the program memory address space at addresses FE00H through FFFFH. PAGE—Page select This 7-bit field identifies the Flash ...
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Flash programming and erasure is not supported for system clock frequencies below Caution: 10 kHz or above 20 MHz. The Flash frequency high and low byte registers must be loaded with the correct value to ensure proper operation of the ...
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PS026308-1207 ® Z8 Encore! F083A Series Product Specification Flash Memory 118 ...
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Flash Option Bits Programmable Flash option bits allow user configuration of certain aspects of Z8 Encore! F083A Series operation. The feature configuration data is stored in the Flash program memory and read during reset. The features available for control through ...
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Option Bit Types User Option Bits The user option bits are contained in the first two bytes of program memory. Your access to these bits is provided because these locations contain application specific device configurations. The information contained here is ...
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Table 76. Trim Bit Address Register (TRMADR BITS FIELD 0 0 RESET R/W R/W R/W ADDR Trim Bit Data Register This register contains the read or write data to access the trim option bits. Table 77. Trim Bit ...
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Flash Program Memory Address 0000H Table 79. Flash Option Bits at Program Memory Address 0000H 7 6 BITS WDT_RES WDT_AO FIELD U U RESET R/W R/W R/W ADDR Note Unchanged by Reset. R/W = Read/Write. WDT_RES—Watchdog Timer reset ...
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FWP—Flash write protect This option bit provides Flash program memory protection Programming and erasure disabled for all Flash program memory. Programming, page erase, and mass erase through user code is disabled. Mass erase is available using the On- ...
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Trim Bit Address Space Table 81. Trim Bit Address Space Address 00h 01h 02h Internal precision oscillator 03h 06h Trim Bit Address 0000H Table 82. Trim Option Bits at 0000H (ADCREF BITS ADCREF_TRIM FIELD RESET R/W ADDR Note: ...
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Reserved —Altering this register may result in incorrect device operation. Note: The bit values used in Trim Bit Address 0002H Table 84. Trim Option Bits at 0002H (TIPO BITS FIELD RESET R/W ADDR Note Unchanged by ...
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VBO Trim Definition VBO_TRIM Trigger Voltage Level 000 001 101 110 100 111 The on-chip Flash only guarantee Write operation with voltage supply over 2.7 V, Write operation below 2.7 V will get unpredictable results. The bit values used in ...
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The bit values used in Note: Table 87. ClkFlt Delay Control Definition DlyCtl3, DlyCtl2, DlyCtl1 000 001 010 011 100 101 110 111 Note: The variation is about 30% PS026308-1207 Table 86 are set at factory and no calibration is ...
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PS026308-1207 ® Z8 Encore! F083A Series Product Specification Flash Option Bits 128 ...
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... This memory can perform over 100,000 write cycles. Operation The NVDS is implemented by special purpose Zilog software stored in areas of program memory not accessible to you. These special purpose routines use the Flash memory to store the data. The routines incorporate a dynamic addressing scheme to maximize the write/erase endurance of the Flash ...
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Write routine ( 0x20B3 working register R0. The bit fields of this status byte are defined in code should pop the address and data bytes off the stack. The write routine uses 16 bytes of stack space in addition to ...
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Because of the Flash memory architecture, NVDS reads exhibit a non-uniform execution time. A read operation takes between 71 μs and 258 μs (assuming a 20 MHz system clock). Slower system clock speeds result in proportionally higher execution times. NVDS ...
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Optimizing NVDS Memory Usage for Execution Speed As listed in Table trade-off for minimizing the frequency of writes that require post-write page erases. The NVDS read time of address function of the number of writes to addresses ...
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On-Chip Debugger The Z8 Encore! devices contain an integrated On-Chip Debugger (OCD) that provides the following advanced debugging features: • Reading and writing of the Register File. • Reading and writing of program and data memory. • Setting of breakpoints ...
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Operation OCD Interface The On-Chip Debugger uses the DBG pin for communication with an external host. This one-pin interface is a bidirectional open-drain interface that transmits and receives data. Data transmission is half-duplex, which means transmission and data retrieval cannot ...
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RS-232 TX RS-232 RX Figure 19. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (2) DEBUG Mode The operating characteristics of the devices in DEBUG mode are: • The eZ8 CPU fetch unit stops, idling the eZ8 CPU, ...
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Asserting the RESET pin low to initiate a reset. • Driving the DBG pin low while the device is in STOP mode, initiates a system reset. OCD Data Format The OCD interface uses the asynchronous data format defined for ...
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OCD Serial Errors The On-Chip Debugger detects any of the following error conditions on the DBG pin: • Serial break (a minimum of nine continuous bits low) • Framing error (received • Transmit collision (simultaneous transmission by OCD and host ...
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On-Chip Debugger Commands The host communicates to the On-Chip Debugger by sending OCD commands using the DBG interface. During normal operation, only a subset of the OCD commands are available. In DEBUG mode, all OCD commands become available unless the ...
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Command Debug Command Execute Instruction Reserved 13H–FFH In the following bulleted list of OCD commands, data and commands sent from the host to the On-Chip Debugger are identified by ‘ Chip Debugger back to the host is identified by ’ ...
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Write Program Counter (06H)—The write program counter command, writes the data that follows to the eZ8 CPU’s program counter (PC). If the device is not in DEBUG mode or if the Flash read protect option bit is enabled, the ...
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DBG Program Memory Address[7:0] ← DBG Size[15:8] ← DBG Size[7:0] ← DBG 1-65536 data bytes • Read Program Memory (0BH)—The read program memory command, reads data from program memory. This command is equivalent to the LDC and LDCI instructions. ...
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DBG 0EH → DBG CRC[15:8] → DBG CRC[7:0] • Step Instruction (10H)—The step instruction command, steps one ...
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Table 92. OCD Control Register (OCDCTL) BITS 7 6 DBGMODE BRKEN FIELD 0 0 RESET R/W R/W R/W DBGMODE—DEBUG mode The device enters DEBUG mode when this bit is 1. When in DEBUG mode, the eZ8 CPU stops fetching ...
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Table 93. OCD Status Register (OCDSTAT) BITS 7 6 DBG HALT FIELD 0 0 RESET R R R/W DBG—Debug status 0 = NORMAL mode 1 = DEBUG mode HALT—HALT Mode 0 = Not in HALT mode HALT ...
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Oscillator Control The Z8 Encore! F083A Series device uses five possible clocking schemes. Each one of these is user-selectable. • On-chip precision trimmed RC oscillator. • On-chip oscillator using off-chip crystal or resonator. • On-chip oscillator using external RC network. ...
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Table 94. Oscillator Configuration and Selection Clock Source Characteristics Internal precision • 119 kHz or 20 MHz RC oscillator • ± 4% accuracy when trimmed • No external components required External crystal/ • 32 kHz to 20 MHz resonator • ...
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When selecting a new clock source, the primary oscillator failure detection circuitry and the Watchdog Timer Oscillator failure circuitry must be disabled. If POFEN and WOFEN are not disabled prior to a clock switch-over possible to generate an ...
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It is possible to disable the clock failure detection circuitry as well as all functioning Caution: clock sources. In this case, the Z8 Encore! F083A Series device ceases functioning and is recovered only by power-on-reset. Oscillator Control Register Definitions Oscillator ...
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WDFEN—Watchdog Timer Oscillator failure detection enable 1 = Failure detection of Watchdog Timer Oscillator is enabled 0 = Failure detection of Watchdog Timer Oscillator is disabled SCKSEL—System clock oscillator select 000 = Internal precision oscillator functions as system clock at ...
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PS026308-1207 ® Z8 Encore! F083A Series Product Specification Oscillator Control 150 ...
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Crystal Oscillator The products in the Z8 Encore! F083A Series contain an on-chip crystal oscillator for use with external crystals with 32 kHz to 20 MHz frequencies. In addition, the oscillator supports external RC networks with oscillation frequencies up to ...
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Printed circuit board layout must add no more than stray capacitance to either the X does not occur, reduce the values of capacitors C XIN ...
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Oscillator Operation with an External RC Network Figure 23 displays a recommended configuration for connection with an external resistor- capacitor (RC) network. Figure 23. Connecting the On-Chip Oscillator to an External RC Network An external resistance value of 45 KΩ ...
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It is possible to operate the RC oscillator using only the parasitic capacitance of the package and printed circuit board. To minimize sensitivity to external parasitics, external capacitance values in excess are recommended. 4000 3750 3500 3250 ...
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Internal Precision Oscillator The internal precision oscillator (IPO) is designed for use without external components. You either manually trim the oscillator for a non-standard frequency or use the automatic factory trimmed version to achieve a 20 MHz frequency with 45%~55% ...
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PS026308-1207 ® Z8 Encore! F083A Series Product Specification Internal Precision Oscillator 156 ...
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CPU Instruction Set Assembly Language Programming Introduction The eZ8 CPU assembly language provides a means for writing an application program without concern for actual memory addresses or machine instruction formats. A program written in assembly language is called a ...
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Assembly Language Syntax For proper instruction execution, eZ8 CPU assembly language syntax requires that the operands be written as ‘destination, source’. After assembly, the object code usually has the operands in the order ‘source, destination’, but ordering is Opcode dependent. ...
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Table 99. Notational Shorthand Notation Description b Bit cc Condition Code DA Direct Address ER Extended Addressing Register IM Immediate Data Ir Indirect Working Register IR Indirect Register Irr Indirect Working Register Pair IRR Indirect Register Pair p Polarity ...
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Table 100 contains additional symbols that are used throughout the instruction summary and instruction set description sections. Table 100. Additional Symbols Symbol Definition dst Destination Operand src Source Operand @ Indirect Address Prefix SP Stack Pointer PC Program Counter FLAGS ...
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Logical • Program control • Rotate and shift Table 101 through number of operands required for each instruction. Some instructions appear in more than one table as these instruction are considered as a subset of more than one category. ...
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Table 102. Bit Manipulation Instructions Mnemonic Operands Instruction BCLR bit, dst BIT p, bit, dst BSET bit, dst BSWAP dst CCF — RCF — SCF — TCM dst, src TCMX dst, src TM dst, src TMX dst, src Table 103. ...
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Table 105. Load Instructions Mnemonic Operands Instruction CLR dst LD dst, src LDC dst, src LDCI dst, src LDE dst, src LDEI dst, src LDWX dst, src LDX dst, src LEA dst, X(src) POP dst POPX dst PUSH src PUSHX ...
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Table 107. Program Control Instructions Mnemonic BRK BTJ BTJNZ BTJZ CALL DJNZ IRET RET TRAP Table 108. Rotate and Shift Instructions Mnemonic BSWAP RL RLC RR RRC SRA SRL SWAP eZ8 CPU Instruction Summary ...
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CPU clock cycles required for the instruction fetch, and the number of CPU clock cycles required for the instruction execution. . Table 109. eZ8 CPU Instruction Summary Assembly Symbolic Mnemonic Operation dst ← dst + src + C ...
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Table 109. eZ8 CPU Instruction Summary (Continued) Assembly Symbolic Mnemonic Operation ATM Block all interrupt and DMA requests during execution of the next 3 instructions dst[bit] ← 0 BCLR bit, dst dst[bit] ← p BIT p, bit, dst BRK Debugger ...
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Table 109. eZ8 CPU Instruction Summary (Continued) Assembly Symbolic Mnemonic Operation CPC dst, src dst - src - C CPCX dst, src dst - src - C CPX dst, src dst - src dst ← DA(dst) DA dst dst ← ...
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Table 109. eZ8 CPU Instruction Summary (Continued) Assembly Symbolic Mnemonic Operation FLAGS ← @SP IRET SP ← ← @SP SP ← IRQCTL[7] ← ← dst JP dst JP cc, dst if ...
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Table 109. eZ8 CPU Instruction Summary (Continued) Assembly Symbolic Mnemonic Operation dst ← src LDEI dst, src r ← ← dst ← src LDWX dst, src dst ← src LDX dst, src dst ...
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Table 109. eZ8 CPU Instruction Summary (Continued) Assembly Symbolic Mnemonic Operation dst ← @SP POP dst SP ← dst ← @SP POPX dst SP ← ← SP – 1 PUSH src @SP ← ...
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Table 109. eZ8 CPU Instruction Summary (Continued) Assembly Symbolic Mnemonic Operation dst ← dst – src - C SBC dst, src dst ← dst – src - C SBCX dst, src C ← 1 SCF SRA dst ...
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Table 109. eZ8 CPU Instruction Summary (Continued) Assembly Symbolic Mnemonic Operation TCM dst, src (NOT dst) AND src TCMX dst, src (NOT dst) AND src TM dst, src dst AND src TMX dst, src dst AND src SP ← SP ...
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Opcode Maps A description of the opcode map data and the abbreviations are provided in Figure 26 on page 175 and eZ8 CPU instructions. Opcode Upper Nibble First Operand After Assembly Figure 25. Opcode Map Cell Description PS026308-1207 Figure 27 ...
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Table 110. Opcode Map Abbreviations Abbreviation Description b Bit position cc Condition code X 8-bit signed index or displacement DA Destination address ER Extended Addressing register IM Immediate data value Ir Indirect Working Register IR Indirect register Irr Indirect Working ...
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BRK SRP ADD ADD 0 IM r1,r2 r1,Ir2 2.2 2.3 2.3 2.4 RLC RLC ADC ADC 1 R1 IR1 r1,r2 r1,Ir2 2.2 2.3 2.3 2.4 INC INC SUB SUB 2 R1 IR1 ...
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PUSH 3.3 3.4 4.3 CPC CPC CPC A r1,r2 r1,Ir2 R2,R1 B 3.2 3.3 SRL SRL C R1 IR1 Figure ...
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Electrical Characteristics The data in this chapter is pre-qualification and pre-characterization and is subject to change. Additional electrical characteristics may be found in the individual chapters. Absolute Maximum Ratings Stresses greater than those listed in These ratings are stress ratings ...
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DC Characteristics Table 112 lists the DC characteristics of the Z8 Encore! F083A Series products. All voltages are referenced to V Table 112. DC Characteristics T A Symbol Parameter Min V Supply Voltage DD V Low Level Input IL1 Voltage ...
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Table 112. DC Characteristics (Continued Symbol Parameter Min I Tristate TL Leakage Current I Controlled LED Current Drive C GPIO Port Pad PAD Capacitance C XIN Pad XIN Capacitance C XOUT Pad XOUT Capacitance I Weak Pull-up PU ...
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V, versus Figure 28 the system clock frequency in HALT mode. Figure 28. ICC Versus System Clock Frequency (HALT mode) PS026308-1207 ® Z8 Encore! F083A Series Product Specification Electrical ...
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Figure 29 NORMAL mode. Figure 29. ICC Versus System Clock Frequency (NORMAL mode) PS026308-1207 ® Z8 Encore! F083A Series Product Specification Electrical Characteristics 181 ...
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AC Characteristics The section provides information about the AC characteristics and timing. All AC timing information assumes a standard load all outputs. Table 113. AC Characteristics Symbol Parameter F System Clock Frequency SYSCLK F Crystal Oscillator ...
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Table 113. AC Characteristics (Continued) Symbol Parameter T Crystal Oscillator Setup XTALSET Time T Internal Precision IPOSET Oscillator Startup Time T WDT Startup Time WDTSET PS026308-1207 3.6 V ...
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On-Chip Peripheral AC and DC Electrical Characteristics Table 114. Power-On Reset and Voltage Brownout Electrical Characteristics and Timing T A Symbol Parameter Min V POR Voltage POR Threshold V Voltage Brownout VBO Reset Voltage Threshold POR VBO ...
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Table 114. Power-On Reset and Voltage Brownout Electrical Characteristics and Timing (Continued Symbol Parameter Min T Stop Mode SMR Recovery with crystal oscillator enabled T Voltage Brownout VBO Pulse Rejection Period T Time for V to RAMP DD ...
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Table 115. Flash Memory Electrical Characteristics and Timing °C to +70 °C A Parameter Min Typ Flash Byte Read Time Flash Byte Program Time Flash Page Erase Time Flash ...
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Table 116. Watchdog Timer Electrical Characteristics and Timing V T Symbol Parameter Min Active power consumption F WDT oscillator WDT frequency Table 117. Non-Volatile Data Storage °C to +70 ...
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Table 118. Analog-to-Digital Converter Electrical Characteristics and Timing Symbol Parameter Min N Resolution DNL Differential 1 Nonlinearity INL Integral 1 Nonlinearity Gain Error Offset Error Vref On chip reference I ADC ADC Active DD Current I ...