STEVAL-IDC001V1 STMicroelectronics, STEVAL-IDC001V1 Datasheet - Page 8

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STEVAL-IDC001V1

Manufacturer Part Number
STEVAL-IDC001V1
Description
BOARD DEVELOPMENT FOR ST72F561
Manufacturer
STMicroelectronics
Type
MCUr
Datasheet

Specifications of STEVAL-IDC001V1

Contents
Board
For Use With/related Products
ST72F561
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8374
STEVAL-IDC001V1
ST7SCR ICC mode entry
Appendix A
A.1
8/10
For an external controller to be able to put the ST7SCR into ICC mode, the procedure has to
be slightly modified because the ST7SCR has no external RESET pin to synchronize the
start of the pulse train that defines ICC mode entry. Instead the synchronization has to be
done on the V
analog comparator with a threshold of 3.8V.
As shown in
Figure 1.
ROM product, ICC mode selection
In ROM ST7SCR devices, the V
this pin is high, the LVD is powered off, pin PA6 becomes a reset pin and pin PA0 becomes
the V
To enter ICC mode:
1.
2.
3.
4.
ICCSEL/V
t
w(pulseH)
t
t
Hold the TM pin at high level.
Reset the chip by applying a low level pulse on PA6
Apply 38 pulses on the PA0 pin as shown in
When the mode entry window is finished, the PA0 port acts as the ICCDATA function.
PP
STARTUP
STARTUP
ICCDATA
ICCCLK
t
pin.
w(pulseL)
f
OSC
V
Entering ICC mode with fixed t
DD
PP
Figure
/2
ST7SCR ICC mode entry
IT+
min. 50 µs +128 t
max. 50 µs +384 t
3.8 V Threshold
rising threshold at power on. This can be implemented by a external
1, a startup delay has to be inserted, specified as follows:
t
h(VppH)
CPU
PP
CPU
t
su(pulse)
38 Pulses within
pin is replaced by a pin called TM (for Test mode). When
t
ST7 internal reset phase
h(pulse)
4096 t
CPU
Figure
window
CPU
1.
t
t
Symbol
t
w(pulseH)
t
w(pulseL)
t
su(pulse)
h(VppH)
h(pulse)
ST7 Flash Programming
+128 clk
ICC monitor execution
50 µs
62.5
Min
+384 clk
50 µs
Max
t
Unit
CPU
ns

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