C8051F005-TB Silicon Laboratories Inc, C8051F005-TB Datasheet - Page 123

• Manufacturer Part Number: C8051F005-TB
• Description: BOARD PROTOTYPING W/C8051F005
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F005-TB

• Contents: Board
• Data Bus Width: 8 bit
• Silicon Manufacturer: Silicon Laboratories
• Core Architecture: 8051
• Silicon Family Name: C8051F00x
• Kit Contents: Board
• Features: JTAG Connector, Debug Adapter Interface, Analog I/O Configuration
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F005
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17. SERIAL PERIPHERAL INTERFACE BUS
The Serial Peripheral Interface (SPI) provides access to a four-wire, full-duplex, serial bus. SPI supports the
connection of multiple slave devices to a master device on the same bus. A separate slave-select signal (NSS) is
used to select a slave device and enable a data transfer between the master and the selected slave. Multiple masters
on the same bus are also supported. Collision detection is provided when two or more masters attempt a data
transfer at the same time. The SPI can operate as either a master or a slave. When the SPI is configured as a
master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency.
When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the
system clock frequency, provided that the master issues SCK, NSS, and the serial input data synchronously with the
system clock. If the master issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer
rate (bits/sec) must be less that 1/10 the system clock frequency. In the special case where the master only wants to
transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the SPI slave
can receive data at a maximum data transfer rate (bits/sec) of ¼ the system clock frequency. This is provided that
the master issues SCK, NSS, and the serial input data synchronously with the system clock.
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C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
SYSCLK
S
C
R
7
S
C
R
6
Clock Divide
SPI0CKR
S
C
R
5
SFR Bus
SPI0DAT
Write to
Logic
S
C
R
4
S
C
R
3
Data Path
Control
S
C
R
2
Receive Data Register
S
C
R
1
7
Figure 17.1. SPI Block Diagram
S
C
R
0
6
Shift Register
5
SPI CONTROL LOGIC
4
C
K
P
H
A
3
O
C
K
P
L
2
(Master Mode)
SFR Bus
SPI0CFG
SPI Clock
B
C
2
1
SPI0DAT
SPI0DAT
Read
Bit Count
B
C
1
0
Logic
B
C
0
Rev. 1.7
F
R
S
2
Tx Data
F
R
S
1
Rx Data
F
R
S
0
Pin Control
S
P
F
Control
I
Interface
Logic
Pin
W
O
C
L
M
O
D
F
SPI0CN
O
R
X
V
R
N
T
X
B
S
Y
MOSI
MISO
SCK
NSS
S
L
V
S
E
L
M
S
T
E
N
S
P
E
N
I
C
R
O
R
S
S
B
A
SPI IRQ
Port I/O