C8051F005-TB Silicon Laboratories Inc, C8051F005-TB Datasheet - Page 156

• Manufacturer Part Number: C8051F005-TB
• Description: BOARD PROTOTYPING W/C8051F005
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F005-TB

• Contents: Board
• Data Bus Width: 8 bit
• Silicon Manufacturer: Silicon Laboratories
• Core Architecture: 8051
• Silicon Family Name: C8051F00x
• Kit Contents: Board
• Features: JTAG Connector, Debug Adapter Interface, Analog I/O Configuration
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F005
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

20.1.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/timer and
load it into the corresponding module’s 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). The CAPPn
and CAPNn bits in the PCA0CPMn register are used to select the type of transition that triggers the capture: low-to-
high transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative
edge). When a capture occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and an interrupt
request is generated if CCF interrupts are enabled. The CCFn bit is not automatically cleared by hardware when the
CPU vectors to the interrupt service routine, and must be cleared by software.
Port I/O
Crossbar
Figure 20.3. PCA Capture Mode Diagram
CEXn
PCA0CPMn
E
C
O
M
n
0
Rev. 1.7
C
A
P
P
n
C
N
A
P
n
0
1
M
A
T
n
0 0 0
O
G
T
n
W
M
P
n
E
C
C
F
n
0
1
C
F
C
R
PCA0CN
C
C
F
4
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
C
C
F
3
PCA
Timebase
C
C
F
2
C
C
F
1
PCA Interrupt
C
C
F
0
Capture
PCA0CPLn
PCA0L
PCA0CPHn
PCA0H
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