C8051F410-TB Silicon Laboratories Inc, C8051F410-TB Datasheet - Page 192

• Manufacturer Part Number: C8051F410-TB
• Description: BOARD PROTOTYPING W/C8051F410
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F410-TB

• Contents: Board
• Processor To Be Evaluated: C8051F41x
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F410
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F410/1/2/3
21.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
21.2. SMBus Configuration
Figure 21.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage
between 3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. The bi-direc-
tional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage
through a pullup resistor or similar circuit. Every device connected to the bus must have an open-drain or
open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive state) when
the bus is free. The maximum number of devices on the bus is limited only by the requirement that the rise
and fall times on the bus not exceed 300 ns and 1000 ns, respectively.
Note: It is recommended that the SDA and SCL pins be configured for high impedance overdrive mode.
See
21.3. SMBus Operation
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave
receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ).
The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The
SMBus interface may operate as a master or a slave, and multiple master devices on the same bus are
supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme
is employed with a single master always winning the arbitration. Note that it is not necessary to specify one
device as the Master in a system; any device who transmits a START and a slave address becomes the
master for the duration of that transfer.
192
Section “18. Port Input/Output” on page 147
1. The I2C Manual (AN10216-01), Philips Semiconductor.
2. System Management Bus Specification -- Version 2, SBS Implementers Forum.
V
Supply
= 5 V
Figure 21.2. Typical SMBus Configuration
V
Supply
Master
Device
= 3 V
Rev. 1.1
for more information.
V
Device 1
Supply
Slave
= 5 V
V
Device 2
Supply
Slave
= 3 V
SDA
SCL