C8051F206DK Silicon Laboratories Inc, C8051F206DK Datasheet - Page 116

DEV KIT FOR C8051F206

C8051F206DK

Manufacturer Part Number
C8051F206DK
Description
DEV KIT FOR C8051F206
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F206DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F206
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051F206
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1237
C8051F2xx
116
Bits7–0: SCR7–SCR0: SPI Clock Rate
These bits determine the frequency of the SCK output when the SPI module is configured for master
Bits7–0: SPI0DAT: SPI0 Transmit and Receive Data.
SCR7
R/W
R/W
Bit7
Bit7
-
mode operation. The SCK clock frequency is a divided down version of the system clock,
and is given in the following equations:
fSCK = 0.5 x fSYSCLK / (SPI0CKR + 1), for 0 < SPI0CKR < 255,
The SPI0DAT register is used to transmit and receive SPI data. Writing data to SPI0DAT
places the data immediately into the shift register and initiates a transfer when in Master
Mode. A read of SPI0DAT returns the contents of the receive buffer.
SCR6
R/W
R/W
Bit6
Bit6
-
SFR Definition 15.3. SPI0CKR: SPI Clock Rate Register
SFR Definition 15.4. SPI0DAT: SPI Data Register
SCR5
R/W
R/W
Bit5
Bit5
-
SCR4
R/W
Bit4
R/W
Bit4
-
SCR3
Rev. 1.6
R/W
Bit3
R/W
Bit3
-
SCR2
R/W
Bit2
R/W
Bit2
-
SCR1
R/W
Bit1
R/W
Bit1
-
SCR0
R/W
Bit0
R/W
Bit0
-
SFR Address:
SFR Address:
Reset Value
Reset Value
00000000
00000000
0x9B
0x9D

Related parts for C8051F206DK