KIT908E624DWBEVB Freescale Semiconductor, KIT908E624DWBEVB Datasheet - Page 36

• Manufacturer Part Number: KIT908E624DWBEVB
• Description: KIT EVAL 908E624 TRPL W/MCU/LIN
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of KIT908E624DWBEVB

• Contents: *
• Silicon Manufacturer: Freescale
• Core Architecture: HC08
• Core Sub-architecture: HC08
• Silicon Core Number: MC68HC908
• Silicon Family Name: HC08E
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 3.0)
INTRODUCTION
technical datasheet. The addendum provides thermal performance information
that may be critical in the design and development of system applications. All
electrical, application, and packaging information is provided in the datasheet.
Packaging and Thermal Considerations
package independently heating with P
temperatures, T
temperature while only heat source 1 is heating with P
reference temperature while heat source 2 is heating with P
R
package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a
package in an application-specific environment. Stated values were obtained by measurement and simulation according to the
standards listed below
Standards
Table 16. Thermal Performance Comparison
36
908E624
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 3.0)
Notes:
θ J21
R
R
R
R
Resistance
This thermal addendum is provided as a supplement to the MM908E624
The MM908E624 is a dual die package. There are two heat sources in the
For m , n = 1, R
For m = 1, n = 2, R
The stated values are solely for a thermal performance comparison of one
θJAmn
θJBmn
θJAmn
θJCmn
1.
2.
3.
4.
5.
Thermal
and R
Per JEDEC JESD51-2 at natural convection, still air
condition.
2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
(1)(2)
(2)(3)
(1)(4)
(5)
θ J22
T
T
J1
J2
J1
, respectively.
θ JA11
and T
m = 1,
=
n = 1
1 = Power Chip, 2 = Logic Chip [°C/ W]
40
25
57
21
θ JA12
is the thermal resistance from Junction 1 to the reference
R
R
J2
θ JA11
θ JA21
, and a thermal resistance matrix with R
is the thermal resistance from Junction 1 to the
R
R
m = 1, n = 2
m = 2, n = 1
θ JA12
θ JA22
31
16
47
12
1
and P
.
P
P
2
1
2
. This results in two junction
m = 2,
n = 2
36
21
52
16
1
.
2
. This applies to
θ JA mn
.
Note For package dimensions, refer to the
MM908E624 datasheet.
17.9 mm x 7.5 mm Body
54 Terminal SOIC
Analog Integrated Circuit Device Data
0.65 mm Pitch
EW (Pb-FREE) SUFFIX
54-TERMINAL SOICW
908E624
54-TERMINAL
98ASA99294D
DWB SUFFIX
SOICW
Freescale Semiconductor