P1020RDB-PA Freescale Semiconductor, P1020RDB-PA Datasheet - Page 25

• Manufacturer Part Number: P1020RDB-PA
• Description: BOARD REFERENCE DESIGN P1020
• Manufacturer: Freescale Semiconductor
• Series: QorlQ™r
• Type: MPUr

Specifications of P1020RDB-PA

• Contents: Board
• For Use With/related Products: P1020
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Shared 256 KB unified frontside L2 cache
w/8-way associativity (each way: 64 KB)
Assignment Granularity:
One, two, four, or all eight “ways” of the
cache can be assigned as the following:
Stash-Only regions can now be defined
Stash Allocate Disable mode added
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data and vice-versa
dedicated as Stash-Only
allocation of new lines
SRAM
Stash-Only
CPU0 L2 Only
CPU1 L2 Only
Both CPU0 and CPU1 L2
Prevents stash data from polluting processor
One, two or four “ways” of the cache can be
Allows update of all resident cache lines without
CPU0 & 1 L2
RD_IN DOUT WR_IN
Stash Only
CPU1 L2
256 KB
25
L2 Cache Controller
Example
128
128
64
Core Complex Bus
w/Parity
I-cache
e500v2 Core
e500 Core 1
32 KB
Coherency
RD1 RD2 WR
e500 Core 0
RD1 RD2 WR
Module
D-cache
w/Parity
32KB
D-cache
w/Parity
32 KB
TM