MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 109

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Please note that the DDR PLL reference clock input, DDRCLK, is only required in asynchronous mode.
The DDRCLKDR configuration register in the Global Utilities block allows the DDR controller to be run in a divided down
mode where the DDR bus clock is half the speed of the default configuration. Changing of these defaults must be completed
prior to initialization of the DDR controller.
2.23.5
The integrated PCI controller in MPC8536E supports PCI input clock frequency in the range of 33–66 MHz. The PCI input
clock can be applied from SYSCLK in synchronous mode or PCI1_CLK in asynchronous mode. For specifications on the
PCI1_CLK, refer to the PCI 2.2 Specification.
The use of PCI1_CLK is optional if SYSCLK is in the range of 33–66 MHz. If SYSCLK is outside this range then use of
PCI1_CLK is required as a separate PCI clock source, asynchronous with respect to SYSCLK.
Freescale Semiconductor
TSEC_1588_TRIG_OUT[0:1],
TSEC1_1588_CLK_OUT
PCI Clocks
Functional Signals
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
Reset Configuration
cfg_ddr_pll[0:2]
Table 77. DDR Clock Ratio
Name
Value (Binary)
000
001
010
011
100
101
110
111
DDR:DDRCLK Ratio
Synchronous mode
Reserved
10:1
12:1
3:1
4:1
6:1
8:1
Clocking
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