DK-SI-4SGX230N Altera, DK-SI-4SGX230N Datasheet - Page 20

• Manufacturer Part Number: DK-SI-4SGX230N
• Description: KIT DEV STRATIX IV 4SGX230N/C2
• Manufacturer: Altera
• Series: Stratix® IV GXr
• Type: FPGAr

Specifications of DK-SI-4SGX230N

• Contents: Board, Cables, CD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2592; DK-SI-4SGX230N/C2

6–6
Transceiver Signal Integrity Development Kit, Stratix IV GX Edition User Guide
Parameter
What statistic to
display?
Inject Error
Data Patrst
Data Rate
GXB Encoding
DataChk Status
CDRLock Mode
Freeze Display
Description
Displays the BER, number of bits received, number of errors received, and the error slope based on the
selection from the list.
The error slope shows the error trend (increase or decrease). You can use this statistic to determine
whether the PMA control settings must be increased or decreased to get an error free link.
Injects errors in the channels. Every time this button is asserted, one-bit error is introduced.
Reset for the data pattern generators and checkers.
Based on the test design selected, the application displays the serial data rate of the transceiver
channels.
Displays whether the data sent by the test design is 8B/10B encoded.
The DataChk Status field displays the following:
■
■
■
Shows whether the transceiver Clock Recovery Unit (CRU) is locked to the reference clock or to the
data. When the transceiver locks to the incoming data, this field displays data indicating that the
receive PLL has recovered the clock from the incoming data.
When you click the Freeze display button, the display field does not change and the counting
continues. When you click the Unfreeze display, the current running values are shown.
Link Statistics Tab
The Link Statistics settings include the following options:
PCI Express Tab
This tab is only available when signal_integrity_demo1.sof is loaded. It provides the
options to control PCI Express (PIPE) parameters for channels 3 and 4 in the middle
transceiver block. Turning on Switch to Gen2 data rate enables the hardware to
change channels 3 and 4 to Gen2 data rate and makes the following options available:
If you have selected the Switch to Gen2 data rate option, set the pre tap and
2ndpost tap to 0 to meet the Gen 2 specification.
Power and Temperature Tab
The application displays the Stratix IV device junction temperature. It also shows the
power or current values for the six supply rails.
■
synced status displayed in green indicates that the error checker has received the predefined header
byte and no errors are detected.
unsynced status displayed in gray indicates that the error checker has not received the selected
pattern.
error status indicates that the error checker is detecting errors in the received pattern.
Parameter
Txdeemphasis
TxMargin
If the DataChk Status field shows unsynced, check whether the transmitter of the channel
showing unsynced is connected to the receiver channel by external cable or by internal serial
loopback. However, when sending the high frequency data pattern, the DataChk Status shows
unsynced. This is because the error checker is not provided for high frequency pattern.
Description
0: –6 db; 1: –3.5 db
0–7
Chapter 6: Stratix IV GX Transceiver Signal Integrity Demonstration
Running the Demonstration Application and Test Designs
© February 2009 Altera Corporation