MPC8378E-MDS-PB Freescale Semiconductor, MPC8378E-MDS-PB Datasheet - Page 126

• Manufacturer Part Number: MPC8378E-MDS-PB
• Description: BOARD PROCESSOR FOR MDS S
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8378E-MDS-PB

• Contents: Board
• For Use With/related Products: MPC8378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document Revision History
126
Revision
2
1
0
10/2009 • In
02/2009 • In
12/2008 Initial public release.
Date
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• Updated part numbering information in AF column in
• In
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
and DDR2 to 600 and 400 μA, respectively. Also, updated Note 1 and added Note 2.
“Min” and “Max”. Footnote 2 updated to state “T is the MCK clock period”.
DDR2 SDRAM Output AC Timing Specifications,” clarified that the frequency parameters are data rates.
parameter values, and the maximum value of SEICx = 01 to 100.
to 150 mV .
to VDD pin.
range to 125–200.
respectively.
rows for SerDes. In addition, changed 666 to 667 MHz.
MHz.
DDR2 SDRAM Output AC Timing Specifications,” and
footnote to references to MVREF, MDQ, and MDQS, referencing AN3665, MPC837xE Design Checklist.
footnote 10 and added footnote 15.
addition, modified extended temperature information in notes 1 and 4.
Table
Table
Section 19.2, “SPI AC Timing Specifications,”
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
27, “SGMII DC Receiver Electrical Characteristics,” updated V
13, “DDR2 SDRAM DC Electrical Characteristics for GV
3, “Recommended Operating Conditions,” added “Operating temperature range” values.
5, “MPC8378E Power Dissipation
5, “MPC8378E Power Dissipation
5, “MPC8378E Power Dissipation
11, removed overbar from CFG_CLKIN_DIV.
17, “Current Draw Characteristics for MV
20, “DDR1 and DDR2 SDRAM Input AC Timing Specifications,” column headings renamed to
20, “DDR1 and DDR2 SDRAM Input AC Timing Specifications,” and
26, “SGMII DC Transmitter Electrical Characteristics,” updated footnote 3.
27, “SGMII DC Receiver Electrical Characteristics,” updated bit name LSTS to SEICx, the
34, “RMII Transmit AC Timing Specifications,” updated t
68, “TePBGA II Pinout
70, “Operating Frequencies for TePBGA
75, “e300 Core PLL Configuration,” added 3.5:1 and 4:1 core_clk: csb_clk ratio options.
76, “Example Clock Frequency Combinations,” updated column heading to “DDR data rate” .
3, “Recommended Operating Conditions,” added two new rows for 800 MHz, and created two
5, “MPC8378E Power Dissipation
21, updated t
68, “TePBGA II Pinout Listing,” added footnote to USBDR_STP_SUSPEND and modified
70, “Operating Frequencies for TePBGA II,” changed 667 to 800 MHz for core_clk.
76, “Example Clock Frequency Combinations,” added 800 MHz cells for e300 core.
81, “Available Parts (Core/DDR Data Rate),” added new row for 800/400 MHz.
Table 83. Document Revision History (continued)
DDKHCX
minimum value for 333 MHz to 2.40.
Listing,”
Substantive Change(s)
removed pin THERM0; it is now Reserved. Also added 1.05 V
1
1
1
1
,” added a column for “Typical Application at T
,” corrected maximal application for 800/400 MHz to 4.3 W.
,” added a column for “Sleep Power at T
,” added Notes 4 and 5. In addition, changed 666 to 667
corrected t
II,”
REF
corrected “DDR2 memory bus frequency (MCK)”
,” updated I
Table
Table
NIKHOX
80, “Part Numbering Nomenclature.” In
68, “TePBGA II Pinout Listing,” added
MVREF
RMTDX
DD
and t
(typ) = 1.8 V,”
LOS
I to 2.0 ns.
NEKHOX
maximum value for both DDR1
maximum value for LSTS =0
Table
Freescale Semiconductor
to t
Table
NIKHOV
21, “DDR1 and
j
= 65°C (W)”.
21, “DDR1 and
j
and t
= 65°C (W)”.
NEKHOV
,