HW-AFX-FF1760-500-G Xilinx Inc, HW-AFX-FF1760-500-G Datasheet - Page 11

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HW-AFX-FF1760-500-G

Manufacturer Part Number
HW-AFX-FF1760-500-G
Description
BOARD DEV VIRTEX 5 FF1760
Manufacturer
Xilinx Inc
Type
FPGAr
Datasheet

Specifications of HW-AFX-FF1760-500-G

Contents
*
For Use With/related Products
Virtex™-5 LX FF1760
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number:
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Virtex-5 LX FPGA Prototype Platform
UG222 (v1.1) April 18, 2008
2. Power Supply Jacks
R
Off Position
Power Enable Jumpers
Table 1: Voltage Ranges
In the OFF position, the power switch disables all modes of powering the DUT.
For each power supply there are headers (J20, J19, and J21) marked REG ENABLE or
REG|JACK. Placement of jumpers on these headers enables delivery of all power from the
onboard regulators. Removing all jumpers allows the user to provide power from the three
power supply jacks marked VCCINT (J33), VCCO (J31), and VCCAUX (J30).
Note:
operation.
One method of delivering power to the DUT is by way of the power supply jacks: VCCINT
(J33), VCCO (J31), and VCCAUX (J30). (Consult the Virtex-5 FPGA Data Sheet: DC and
Switching Characteristics
power supply jacks are:
VCCINT
VCCO
VCCAUX
VCC1V8
VCCINT
VCCO
VCCAUX
Label
If using an external bench top power supply, 5V must be applied to the 5V jack, J32, for proper
Supplies voltage to the V
Supplies I/O voltages to the DUT
Each bank can be powered from one of two sources (V
appropriate placement of jumpers on the header
Supplies voltage to the V
Maximum Voltage
[Ref 1]
1.0V
2.5V
2.5V
1.8V
www.xilinx.com
for the maximum voltage rating for each device.) The
CCINT
CCAUX
of the DUT
DUT pins
Maximum Current
7A
4A
3A
3A
CCO
, V
Detailed Description
CCINT
) by
11

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